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| author |   Chen Wang <unicorn_wang@outlook.com> | 2023-10-04 23:42:23 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-10-06 14:36:54 +0100 |
| commit | b965d9a965943e5c07bdda0734aaeecca9ab86b3 (patch) | |
| tree | cce9f73dd0d1323fa22b381e30b14644be2bbd22 | |
| parent | dt-bindings: riscv: add sophgo sg2042 bindings (diff) | |
| download | wireguard-linux-b965d9a965943e5c07bdda0734aaeecca9ab86b3.tar.xz wireguard-linux-b965d9a965943e5c07bdda0734aaeecca9ab86b3.zip | |
dt-bindings: riscv: Add T-HEAD C920 compatibles
The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C920 core is used in the SOPHGO's SG2042 SoC.
Acked-by: Chao Wei <chao.wei@sophgo.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 38c0b5213736..185a0191bad6 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -47,6 +47,7 @@ properties: - sifive,u74-mc - thead,c906 - thead,c910 + - thead,c920 - const: riscv - items: - enum: |