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authorJonathan Marek <jonathan@marek.ca>2021-06-17 10:43:34 -0400
committerRob Clark <robdclark@chromium.org>2021-08-07 11:48:37 -0700
commitbb5b94f5bbe75470912b70fb08880fc5273aa62d (patch)
tree981a44079f61602c4ba548c942f8028ee09a4fa0
parentdt-bindings: msm: dsi: add missing 7nm bindings (diff)
downloadwireguard-linux-bb5b94f5bbe75470912b70fb08880fc5273aa62d.tar.xz
wireguard-linux-bb5b94f5bbe75470912b70fb08880fc5273aa62d.zip
dt-bindings: msm: dsi: document phy-type property for 7nm dsi phy
Document a new phy-type property which will be used to determine whether the phy should operate in D-PHY or C-PHY mode. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210617144349.28448-3-jonathan@marek.ca Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
-rw-r--r--Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml5
-rw-r--r--include/dt-bindings/phy/phy.h2
2 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
index c0077ca7e9e7..70809d1cac54 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
@@ -34,6 +34,11 @@ properties:
description: |
Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
+ phy-type:
+ description: D-PHY (default) or C-PHY mode
+ enum: [ 10, 11 ]
+ default: 10
+
required:
- compatible
- reg
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index 887a31b250a8..f48c9acf251e 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -20,5 +20,7 @@
#define PHY_TYPE_XPCS 7
#define PHY_TYPE_SGMII 8
#define PHY_TYPE_QSGMII 9
+#define PHY_TYPE_DPHY 10
+#define PHY_TYPE_CPHY 11
#endif /* _DT_BINDINGS_PHY */