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| author |   Thierry Reding <treding@nvidia.com> | 2020-03-19 16:45:38 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2021-12-16 16:51:01 +0100 |
| commit | bd1fefcbdd8f1791c9a0e8dd169006c2a466cf17 (patch) | |
| tree | facd7d5c9ca7945819a8bd1d9f872b8fe4eb43a3 | |
| parent | arm64: tegra: Rename top-level regulators (diff) | |
| download | wireguard-linux-bd1fefcbdd8f1791c9a0e8dd169006c2a466cf17.tar.xz wireguard-linux-bd1fefcbdd8f1791c9a0e8dd169006c2a466cf17.zip | |
arm64: tegra: Add native timer support on Tegra186
The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index fe588666bcfc..855ae6b705a8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -508,6 +508,22 @@ }; }; + timer@3010000 { + compatible = "nvidia,tegra186-timer"; + reg = <0x0 0x03010000 0x0 0x000e0000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; |