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author | 2024-05-03 15:29:14 -0400 | |
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committer | 2024-06-17 10:38:17 +0300 | |
commit | c194dd025ae9e5b2c99056200f1e39494919a6cb (patch) | |
tree | 437a1273c9671b1b77f281bf6d56178d4c280263 | |
parent | drm: zynqmp_kms: Fix AUX bus not getting unregistered (diff) | |
download | wireguard-linux-c194dd025ae9e5b2c99056200f1e39494919a6cb.tar.xz wireguard-linux-c194dd025ae9e5b2c99056200f1e39494919a6cb.zip |
drm: zynqmp_dp: Rearrange zynqmp_dp for better padding
Sort the members of struct zynqmp_dp to reduce padding necessary for
alignment.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240503192922.2172314-3-sean.anderson@linux.dev
-rw-r--r-- | drivers/gpu/drm/xlnx/zynqmp_dp.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 9df068a413f3..12a8248ed125 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -256,10 +256,10 @@ struct zynqmp_dp_link_config { * @fmt: format identifier string */ struct zynqmp_dp_mode { + const char *fmt; + int pclock; u8 bw_code; u8 lane_cnt; - int pclock; - const char *fmt; }; /** @@ -296,27 +296,27 @@ struct zynqmp_dp_config { * @train_set: set of training data */ struct zynqmp_dp { + struct drm_dp_aux aux; + struct drm_bridge bridge; + struct delayed_work hpd_work; + + struct drm_bridge *next_bridge; struct device *dev; struct zynqmp_dpsub *dpsub; void __iomem *iomem; struct reset_control *reset; - int irq; - - struct drm_bridge bridge; - struct drm_bridge *next_bridge; - - struct zynqmp_dp_config config; - struct drm_dp_aux aux; struct phy *phy[ZYNQMP_DP_MAX_LANES]; - u8 num_lanes; - struct delayed_work hpd_work; + enum drm_connector_status status; + int irq; bool enabled; - u8 dpcd[DP_RECEIVER_CAP_SIZE]; - struct zynqmp_dp_link_config link_config; struct zynqmp_dp_mode mode; + struct zynqmp_dp_link_config link_config; + struct zynqmp_dp_config config; + u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 train_set[ZYNQMP_DP_MAX_LANES]; + u8 num_lanes; }; static inline struct zynqmp_dp *bridge_to_dp(struct drm_bridge *bridge) |