diff options
| author |   Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-03-21 16:46:27 +0530 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2024-04-21 12:31:41 -0500 |
| commit | cf3e010d7f4c20d3a82fb07feb937fd771cb1b53 (patch) | |
| tree | a2451f14899f1687c844d4bda955f72b91fcec28 | |
| parent | arm64: dts: qcom: sm8550: Add PCIe bridge node (diff) | |
| download | wireguard-linux-cf3e010d7f4c20d3a82fb07feb937fd771cb1b53.tar.xz wireguard-linux-cf3e010d7f4c20d3a82fb07feb937fd771cb1b53.zip | |
arm64: dts: qcom: sm8650: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-7-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 89d6424a2b05..434ad2f12332 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2294,6 +2294,16 @@ dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2422,6 +2432,16 @@ <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { |