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| author |   Sascha Hauer <s.hauer@pengutronix.de> | 2023-10-18 08:17:00 +0200 |
|---|---|---|
| committer |   Chanwoo Choi <cw00.choi@samsung.com> | 2023-10-19 20:48:28 +0900 |
| commit | d8c6e337e71d3aa05414d8a06a4ff19d45c7be36 (patch) | |
| tree | 6e425f7641edf99313184297e0fce3bc22a1cb55 | |
| parent | PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly (diff) | |
| download | wireguard-linux-d8c6e337e71d3aa05414d8a06a4ff19d45c7be36.tar.xz wireguard-linux-d8c6e337e71d3aa05414d8a06a4ff19d45c7be36.zip | |
PM / devfreq: rockchip-dfi: Handle LPDDR4X
In the DFI driver LPDDR4X can be handled in the same way as LPDDR4. Add
the missing case.
Link: https://lore.kernel.org/all/20231018061714.3553817-13-s.hauer@pengutronix.de/
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
| -rw-r--r-- | drivers/devfreq/event/rockchip-dfi.c | 1 | ||||
| -rw-r--r-- | include/soc/rockchip/rockchip_grf.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 8ce0191552ef..bdf421b248df 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -90,6 +90,7 @@ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) dfi_regs + DDRMON_CTRL); break; case ROCKCHIP_DDRTYPE_LPDDR4: + case ROCKCHIP_DDRTYPE_LPDDR4X: writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), dfi_regs + DDRMON_CTRL); break; diff --git a/include/soc/rockchip/rockchip_grf.h b/include/soc/rockchip/rockchip_grf.h index dde1a9796ccb..e46fd72aea8d 100644 --- a/include/soc/rockchip/rockchip_grf.h +++ b/include/soc/rockchip/rockchip_grf.h @@ -12,6 +12,7 @@ enum { ROCKCHIP_DDRTYPE_LPDDR2 = 5, ROCKCHIP_DDRTYPE_LPDDR3 = 6, ROCKCHIP_DDRTYPE_LPDDR4 = 7, + ROCKCHIP_DDRTYPE_LPDDR4X = 8, }; #endif /* __SOC_ROCKCHIP_GRF_H */ |