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| author |   Allen-KH Cheng <allen-kh.cheng@mediatek.com> | 2022-04-21 11:51:10 +0800 |
|---|---|---|
| committer |   Matthias Brugger <matthias.bgg@gmail.com> | 2022-04-26 10:58:57 +0200 |
| commit | dab2782be22c359dd1a14a118e9b1592a7f91db3 (patch) | |
| tree | cf99ccdbc39c8a0645ecc2acbfdb484d5493598a | |
| parent | arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes (diff) | |
| download | wireguard-linux-dab2782be22c359dd1a14a118e9b1592a7f91db3.tar.xz wireguard-linux-dab2782be22c359dd1a14a118e9b1592a7f91db3.zip | |
arm64: dts: mediatek: mt8173: Add power domain to encoder nodes
The power of encoder is not control by mediatek,larb, so we add
power domain to encoder nodes for mt8173 SoC.
Signed-off-by: Irui Wang <irui.wang@mediatek.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Link: https://lore.kernel.org/r/20220421035111.7267-4-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 10291b2690ab..eebc2d074254 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1470,6 +1470,7 @@ clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; }; jpegdec: jpegdec@18004000 { @@ -1520,6 +1521,7 @@ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; }; }; }; |