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| author |   Jiaxun Yang <jiaxun.yang@flygoat.com> | 2023-04-04 10:33:42 +0100 |
|---|---|---|
| committer |   Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-04-05 09:45:08 +0200 |
| commit | e1aa1dfef69320141f5d00eddbf279b41e70d4e7 (patch) | |
| tree | cb043443d12298336787df2c5f2c7d29958f62e5 | |
| parent | MIPS: smp-cps: Disable coherence setup for unsupported ISA (diff) | |
| download | wireguard-linux-e1aa1dfef69320141f5d00eddbf279b41e70d4e7.tar.xz wireguard-linux-e1aa1dfef69320141f5d00eddbf279b41e70d4e7.zip | |
MIPS: mips-cm: Check availability of config registers
Prevent reading unsupported config register during probing process.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| -rw-r--r-- | arch/mips/kernel/mips-cm.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index b4f7d950c846..3f00788b0871 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -181,11 +181,16 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags); phys_addr_t __mips_cm_phys_base(void) { - u32 config3 = read_c0_config3(); unsigned long cmgcr; /* Check the CMGCRBase register is implemented */ - if (!(config3 & MIPS_CONF3_CMGCR)) + if (!(read_c0_config() & MIPS_CONF_M)) + return 0; + + if (!(read_c0_config2() & MIPS_CONF_M)) + return 0; + + if (!(read_c0_config3() & MIPS_CONF3_CMGCR)) return 0; /* Read the address from CMGCRBase */ |