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| author |   Mika Westerberg <mika.westerberg@linux.intel.com> | 2020-01-22 19:46:11 +0300 |
|---|---|---|
| committer |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2020-01-22 18:52:26 +0200 |
| commit | e1f461631123fa808ff1d1fca5f39cee21085143 (patch) | |
| tree | 6ad95a58cceabf62b98c0df68c23392cbd15e148 | |
| parent | platform/x86: intel_scu_ipc: Reformat kernel-doc comments of exported functions (diff) | |
| download | wireguard-linux-e1f461631123fa808ff1d1fca5f39cee21085143.tar.xz wireguard-linux-e1f461631123fa808ff1d1fca5f39cee21085143.zip | |
platform/x86: intel_pmc_ipc: Make intel_pmc_gcr_update() static
This function is not called outside of intel_pmc_ipc.c so we can make it
static instead.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| -rw-r--r-- | arch/x86/include/asm/intel_pmc_ipc.h | 6 | ||||
| -rw-r--r-- | drivers/platform/x86/intel_pmc_ipc.c | 3 |
2 files changed, 1 insertions, 8 deletions
diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h index 9e7adcdbe031..3b2e8b461520 100644 --- a/arch/x86/include/asm/intel_pmc_ipc.h +++ b/arch/x86/include/asm/intel_pmc_ipc.h @@ -40,7 +40,6 @@ int intel_pmc_s0ix_counter_read(u64 *data); int intel_pmc_gcr_read(u32 offset, u32 *data); int intel_pmc_gcr_read64(u32 offset, u64 *data); int intel_pmc_gcr_write(u32 offset, u32 data); -int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val); #else @@ -81,11 +80,6 @@ static inline int intel_pmc_gcr_write(u32 offset, u32 data) return -EINVAL; } -static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) -{ - return -EINVAL; -} - #endif /*CONFIG_INTEL_PMC_IPC*/ #endif diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index 5c1da2bb1435..9229c7a16536 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -309,7 +309,7 @@ EXPORT_SYMBOL_GPL(intel_pmc_gcr_write); * * Return: negative value on error or 0 on success. */ -int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) +static int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) { u32 new_val; int ret = 0; @@ -339,7 +339,6 @@ gcr_ipc_unlock: spin_unlock(&ipcdev.gcr_lock); return ret; } -EXPORT_SYMBOL_GPL(intel_pmc_gcr_update); static int update_no_reboot_bit(void *priv, bool set) { |