diff options
| author |   Rashmica Gupta <rashmica@linux.ibm.com> | 2022-06-17 14:31:35 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2022-07-28 16:22:14 +1000 |
| commit | e4787e71ae2de3f60bc04fe09d1be4ef628b6c68 (patch) | |
| tree | 99ec2df994e0ef313402f8e94a3b86647d7916aa | |
| parent | powerpc: make facility_unavailable_exception 64s (diff) | |
| download | wireguard-linux-e4787e71ae2de3f60bc04fe09d1be4ef628b6c68.tar.xz wireguard-linux-e4787e71ae2de3f60bc04fe09d1be4ef628b6c68.zip | |
powerpc/signal: Update comment for clarity
The comment being referred to was deleted in commit af1bbc3dd3d5 ("powerpc:
Remove UP only lazy floating point and vector optimisations").
Add a bit more detail so it's clear why we need to clear the FP/VEC/VSX
bits here.
Signed-off-by: Rashmica Gupta <rashmica@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220617043135.426897-1-rashmica@linux.ibm.com
| -rw-r--r-- | arch/powerpc/kernel/signal_64.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index 472596a109e2..86bb5bb4c143 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c @@ -377,9 +377,12 @@ static long notrace __unsafe_restore_sigcontext(struct task_struct *tsk, sigset_ unsafe_get_user(set->sig[0], &sc->oldmask, efault_out); /* - * Force reload of FP/VEC. - * This has to be done before copying stuff into tsk->thread.fpr/vr - * for the reasons explained in the previous comment. + * Force reload of FP/VEC/VSX so userspace sees any changes. + * Clear these bits from the user process' MSR before copying into the + * thread struct. If we are rescheduled or preempted and another task + * uses FP/VEC/VSX, and this process has the MSR bits set, then the + * context switch code will save the current CPU state into the + * thread_struct - possibly overwriting the data we are updating here. */ regs_set_return_msr(regs, regs->msr & ~(MSR_FP | MSR_FE0 | MSR_FE1 | MSR_VEC | MSR_VSX)); |