diff options
| author |   Gustavo Sousa <gustavo.sousa@intel.com> | 2024-01-05 11:05:37 -0300 |
|---|---|---|
| committer |   Matt Roper <matthew.d.roper@intel.com> | 2024-01-08 10:55:46 -0800 |
| commit | ebb9c4240deaaa54b70926bdc4d4ceb22518c0cb (patch) | |
| tree | 3bb4b4719df03fb952a5d161cd1efb277e855481 | |
| parent | drm/i915/cdclk: Extract bxt_cdclk_ctl() (diff) | |
| download | wireguard-linux-ebb9c4240deaaa54b70926bdc4d4ceb22518c0cb.tar.xz wireguard-linux-ebb9c4240deaaa54b70926bdc4d4ceb22518c0cb.zip | |
drm/i915/cdclk: Reorder bxt_sanitize_cdclk()
Make the sequence of steps in bxt_sanitize_cdclk() more logical by
grouping things related to the check on the value of CDCLK_CTL into a
single "block". Also, this will make an upcoming change replacing that
block with a single function call easier to follow.
v2:
- Improve body of commit message to be more self-contained.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240105140538.183553-4-gustavo.sousa@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index b9354ad46fee..fbe9aba41c35 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2060,13 +2060,23 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) goto sanitize; - /* DPLL okay; verify the cdclock - * + /* Make sure this is a legal cdclk value for the platform */ + cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); + if (cdclk != dev_priv->display.cdclk.hw.cdclk) + goto sanitize; + + /* Make sure the VCO is correct for the cdclk */ + vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); + if (vco != dev_priv->display.cdclk.hw.vco) + goto sanitize; + + /* * Some BIOS versions leave an incorrect decimal frequency value and * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, * so sanitize this register. */ cdctl = intel_de_read(dev_priv, CDCLK_CTL); + /* * Let's ignore the pipe field, since BIOS could have configured the * dividers both synching to an active pipe, or asynchronously @@ -2074,16 +2084,6 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) */ cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); - /* Make sure this is a legal cdclk value for the platform */ - cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); - if (cdclk != dev_priv->display.cdclk.hw.cdclk) - goto sanitize; - - /* Make sure the VCO is correct for the cdclk */ - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); - if (vco != dev_priv->display.cdclk.hw.vco) - goto sanitize; - if (DISPLAY_VER(dev_priv) >= 20) expected = MDCLK_SOURCE_SEL_CDCLK_PLL; else |