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| author |   Dmitry Osipenko <digetx@gmail.com> | 2020-11-04 19:48:45 +0300 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzk@kernel.org> | 2020-11-06 19:31:25 +0100 |
| commit | ed7f6f2eaae850ee836bee05feb1df722c13efad (patch) | |
| tree | 3f326f04bd6914c1d193620dd226a464960a1286 | |
| parent | dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator (diff) | |
| download | wireguard-linux-ed7f6f2eaae850ee836bee05feb1df722c13efad.tar.xz wireguard-linux-ed7f6f2eaae850ee836bee05feb1df722c13efad.zip | |
dt-bindings: memory: tegra30: mc: Document new interconnect property
Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201104164923.21238-10-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml index 84fd57bcf0dc..5436e6d420bc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -57,6 +57,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -120,6 +123,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -135,6 +139,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-1 { nvidia,ram-code = <1>; |