diff options
| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-26 12:18:36 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-26 12:18:36 -0800 |
| commit | f3a2439f20d918930cc4ae8f76fe1c1afd26958f (patch) | |
| tree | b74738bccf65a4d50dd908859537fd39ca13c922 | |
| parent | Merge tag 'rpmsg-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux (diff) | |
| parent | dt-bindings: mailbox: qcom,apcs-kpss-global: drop mbox-names from example (diff) | |
| download | wireguard-linux-f3a2439f20d918930cc4ae8f76fe1c1afd26958f.tar.xz wireguard-linux-f3a2439f20d918930cc4ae8f76fe1c1afd26958f.zip | |
Merge tag 'rproc-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
Pull remoteproc updates from Bjorn Andersson:
- Support for PRU clients to acquire a control reference to the PRU
instances is introduced, and the PRU now allows specifying
firmware-name in Devicetree. sysfs is requested to be read-only when
the remoteproc instance is consumed by another kernel driver
- Support for the C7xv DSP on AM62A SoC is introduced
- The Devicetree binding for the Qualcomm PAS devices are split up in
multiple files, to better account for the differences in resources
between them. A number of missing Devicetree bindings are added, and
the Qualcomm WCNSS binding is converted to YAML
- A few cleanups are introduced for the Mediatek SCP driver. And a
sanity check of the firmware image is introduced in the Mediatek
driver
- For Qualcomm SC7280 ADSP support is added, MSM8953 gains ADSP and
modem support, SM6115 and SM8550 gains ADSP, CDSP and modem support,
and support for pronto v3 support (used on e.g. MSM8953) is added
- The Qualcomm modem remoteproc driver is modified to use a no-map
reserved-memory region for it's authentication metadata, in order to
avoid fatal security violations caused by accesses from Linux during
the authentication process
- Support for separate loading of a Devicetree blob is added to the PAS
driver, and support for the PAS driver to carve out DSM memory for
the modem is added as well
- The Qualcomm ADSP remoteproc driver gains support for mapping memory
into specific range using the IOMMU. The sysmon driver is
transitioned to strlcpy()
* tag 'rproc-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (69 commits)
dt-bindings: mailbox: qcom,apcs-kpss-global: drop mbox-names from example
dt-bindings: remoteproc: qcom,glink-edge: correct label description
dt-bindings: remoteproc: qcom,glink-rpm-edge: convert to DT schema
dt-bindings: remoteproc: qcom,sm8550-pas: correct power domains
remoteproc: qcom_q6v5_pas: enable sm8550 adsp & cdsp autoboot
dt-bindings: remoteproc: qcom: Add sm6115 pas yaml file
remoteproc: qcom: pas: Add sm6115 remoteprocs
remoteproc: qcom: pas: Adjust the phys addr wrt the mem region
remoteproc: qcom: fix sparse warnings
remoteproc: qcom: replace kstrdup with kstrndup
remoteproc: mediatek: Check the SCP image format
remoteproc: qcom_q6v5_mss: Use a carveout to authenticate modem headers
Revert "remoteproc: qcom_q6v5_mss: map/unmap metadata region before/after use"
dt-bindings: remoteproc: qcom,sc7280-mss-pil: Update memory-region
dt-bindings: remoteproc: qcom,sc7180-mss-pil: Update memory-region
dt-bindings: remoteproc: qcom,msm8996-mss-pil: Update memory region
dt-bindings: remoteproc: qcom,q6v5: Move MSM8996 to schema
remoteproc: qcom_q6v5_pas: add sm8550 adsp, cdsp & mpss compatible & data
remoteproc: qcom_q6v5_pas: add support for assigning memory to firmware
remoteproc: qcom_q6v5_pas: add support for dtb co-firmware loading
...
38 files changed, 3738 insertions, 912 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 658d03aa0349..d888ead09282 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -180,7 +180,6 @@ examples: interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,rpm-msg-ram = <&rpm_msg_ram>; mboxes = <&apcs_glb 0>; - mbox-names = "rpm_hlos"; }; # Example apcs with qcs404 diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index c1d9cbc359b4..643ee787a81f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -17,201 +17,52 @@ properties: compatible: enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas - - qcom,qcs404-adsp-pas - - qcom,qcs404-cdsp-pas - - qcom,qcs404-wcss-pas - - qcom,sc7180-mpss-pas - - qcom,sc7280-mpss-pas - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8180x-mpss-pas - - qcom,sc8280xp-adsp-pas - - qcom,sc8280xp-nsp0-pas - - qcom,sc8280xp-nsp1-pas - qcom,sdm660-adsp-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - - qcom,sdx55-mpss-pas - - qcom,sm6350-adsp-pas - - qcom,sm6350-cdsp-pas - - qcom,sm6350-mpss-pas - - qcom,sm8150-adsp-pas - - qcom,sm8150-cdsp-pas - - qcom,sm8150-mpss-pas - - qcom,sm8150-slpi-pas - - qcom,sm8250-adsp-pas - - qcom,sm8250-cdsp-pas - - qcom,sm8250-slpi-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-mpss-pas - - qcom,sm8450-slpi-pas reg: maxItems: 1 - clocks: - minItems: 1 - maxItems: 8 - - clock-names: - minItems: 1 - maxItems: 8 - - interconnects: - maxItems: 1 - - interrupts: - minItems: 5 - items: - - description: Watchdog interrupt - - description: Fatal interrupt - - description: Ready interrupt - - description: Handover interrupt - - description: Stop acknowledge interrupt - - description: Shutdown acknowledge interrupt - - interrupt-names: - minItems: 5 - items: - - const: wdog - - const: fatal - - const: ready - - const: handover - - const: stop-ack - - const: shutdown-ack - - resets: - minItems: 1 - maxItems: 3 - - reset-names: - minItems: 1 - maxItems: 3 - cx-supply: description: Phandle to the CX regulator px-supply: description: Phandle to the PX regulator - power-domains: - minItems: 1 - maxItems: 3 - - power-domain-names: - minItems: 1 - maxItems: 3 - - firmware-name: - $ref: /schemas/types.yaml#/definitions/string - description: Firmware name for the Hexagon core - - memory-region: - maxItems: 1 - description: Reference to the reserved-memory for the Hexagon core - qcom,qmp: $ref: /schemas/types.yaml#/definitions/phandle description: Reference to the AOSS side-channel message RAM. - qcom,smem-states: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: States used by the AP to signal the Hexagon core - items: - - description: Stop the modem - - qcom,smem-state-names: - description: The names of the state bits used for SMP2P output - items: - - const: stop - - qcom,halt-regs: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: Phandle reference to a syscon representing TCSR - - description: offsets within syscon for q6 halt registers - - description: offsets within syscon for modem halt registers - - description: offsets within syscon for nc halt registers - description: - Phandle reference to a syscon representing TCSR followed by the - three offsets within syscon for q6, modem and nc halt registers. - - smd-edge: - $ref: /schemas/remoteproc/qcom,smd-edge.yaml# - description: - Qualcomm Shared Memory subnode which represents communication edge, - channels and devices related to the ADSP. - unevaluatedProperties: false - - glink-edge: - $ref: /schemas/remoteproc/qcom,glink-edge.yaml# - description: - Qualcomm G-Link subnode which represents communication edge, channels - and devices related to the ADSP. + memory-region: + maxItems: 1 + description: Reference to the reserved-memory for the Hexagon core required: - compatible - - clocks - - clock-names - - interrupts - - interrupt-names - - memory-region - - qcom,smem-states - - qcom,smem-state-names -additionalProperties: false +unevaluatedProperties: false allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# - if: properties: compatible: contains: enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - - qcom,qcs404-adsp-pas - - qcom,qcs404-wcss-pas - - qcom,sc7280-mpss-pas - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8180x-mpss-pas - - qcom,sc8280xp-adsp-pas - - qcom,sc8280xp-nsp0-pas - - qcom,sc8280xp-nsp1-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - - qcom,sm6350-adsp-pas - - qcom,sm6350-cdsp-pas - - qcom,sm6350-mpss-pas - - qcom,sm8150-adsp-pas - - qcom,sm8150-cdsp-pas - - qcom,sm8150-mpss-pas - - qcom,sm8150-slpi-pas - - qcom,sm8250-adsp-pas - - qcom,sm8250-cdsp-pas - - qcom,sm8250-slpi-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-slpi-pas - - qcom,sm8450-mpss-pas then: properties: clocks: @@ -226,6 +77,7 @@ allOf: compatible: contains: enum: + - qcom,msm8996-slpi-pil - qcom,msm8998-slpi-pas then: properties: @@ -243,90 +95,15 @@ allOf: compatible: contains: enum: - - qcom,qcs404-cdsp-pas - then: - properties: - clocks: - items: - - description: XO clock - - description: SWAY clock - - description: TBU clock - - description: BIMC clock - - description: AHB AON clock - - description: Q6SS SLAVE clock - - description: Q6SS MASTER clock - - description: Q6 AXIM clock - clock-names: - items: - - const: xo - - const: sway - - const: tbu - - const: bimc - - const: ahb_aon - - const: q6ss_slave - - const: q6ss_master - - const: q6_axim - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc7180-mpss-pas - then: - properties: - clocks: - items: - - description: XO clock - - description: IFACE clock - - description: BUS clock - - description: NAC clock - - description: SNOC AXI clock - - description: MNOC AXI clock - clock-names: - items: - - const: xo - - const: iface - - const: bus - - const: nav - - const: snoc_axi - - const: mnoc_axi - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas - - qcom,qcs404-adsp-pas - - qcom,qcs404-cdsp-pas - - qcom,qcs404-wcss-pas - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8280xp-adsp-pas - - qcom,sc8280xp-nsp0-pas - - qcom,sc8280xp-nsp1-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - - qcom,sm6350-adsp-pas - - qcom,sm6350-cdsp-pas - - qcom,sm8150-adsp-pas - - qcom,sm8150-cdsp-pas - - qcom,sm8150-slpi-pas - - qcom,sm8250-adsp-pas - - qcom,sm8250-cdsp-pas - - qcom,sm8250-slpi-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-cdsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-cdsp-pas - - qcom,sm8450-slpi-pas then: properties: interrupts: @@ -339,26 +116,6 @@ allOf: compatible: contains: enum: - - qcom,sc7180-mpss-pas - - qcom,sc7280-mpss-pas - - qcom,sc8180x-mpss-pas - - qcom,sdx55-mpss-pas - - qcom,sm6350-mpss-pas - - qcom,sm8150-mpss-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-mpss-pas - then: - properties: - interrupts: - minItems: 6 - interrupt-names: - minItems: 6 - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8974-adsp-pil then: required: @@ -370,10 +127,9 @@ allOf: contains: enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8998-adsp-pas - - qcom,sm8150-adsp-pas - - qcom,sm8150-cdsp-pas then: properties: power-domains: @@ -406,169 +162,14 @@ allOf: compatible: contains: enum: - - qcom,sc7180-mpss-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MX power domain - - description: MSS power domain - power-domain-names: - items: - - const: cx - - const: mx - - const: mss - - - if: - properties: - compatible: - contains: - enum: - - qcom,sm6350-cdsp-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MX power domain - power-domain-names: - items: - - const: cx - - const: mx - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc7280-mpss-pas - - qcom,sdx55-mpss-pas - - qcom,sm6350-mpss-pas - - qcom,sm8150-mpss-pas - - qcom,sm8350-mpss-pas - - qcom,sm8450-mpss-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MSS power domain - power-domain-names: - items: - - const: cx - - const: mss - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8280xp-adsp-pas - - qcom,sm6350-adsp-pas - - qcom,sm8150-slpi-pas - - qcom,sm8250-adsp-pas - - qcom,sm8250-slpi-pas - - qcom,sm8350-adsp-pas - - qcom,sm8350-slpi-pas - - qcom,sm8450-adsp-pas - - qcom,sm8450-slpi-pas - then: - properties: - power-domains: - items: - - description: LCX power domain - - description: LMX power domain - power-domain-names: - items: - - const: lcx - - const: lmx - - - if: - properties: - compatible: - contains: - enum: - - qcom,sm8350-cdsp-pas - - qcom,sm8450-cdsp-pas - then: - properties: - power-domains: - items: - - description: CX power domain - - description: MXC power domain - power-domain-names: - items: - - const: cx - - const: mxc - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8280xp-nsp0-pas - - qcom,sc8280xp-nsp1-pas - then: - properties: - power-domains: - items: - - description: NSP power domain - power-domain-names: - items: - - const: nsp - - - if: - properties: - compatible: - contains: - enum: - - qcom,qcs404-cdsp-pas - then: - properties: - resets: - items: - - description: CDSP restart - reset-names: - items: - - const: restart - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc7180-mpss-pas - - qcom,sc7280-mpss-pas - then: - properties: - resets: - items: - - description: MSS restart - - description: PDC reset - reset-names: - items: - - const: mss_restart - - const: pdc_reset - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8226-adsp-pil + - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil - qcom,msm8998-adsp-pas - qcom,msm8998-slpi-pas - - qcom,qcs404-adsp-pas - - qcom,qcs404-cdsp-pas - - qcom,qcs404-wcss-pas - qcom,sdm660-adsp-pas - - qcom,sdx55-mpss-pas then: properties: qcom,qmp: false diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml index 8e133ab55ff3..15e6851e1ff8 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml @@ -42,7 +42,9 @@ properties: maxItems: 1 label: - description: The names of the state bits used for SMP2P output + description: + Name of the edge, used for debugging and identification purposes. The + node name will be used if this is not present. mboxes: maxItems: 1 diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml new file mode 100644 index 000000000000..6e6e69ad9cd7 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml @@ -0,0 +1,289 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,msm8916-mss-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8916 MSS Peripheral Image Loader (and similar) + +maintainers: + - Stephan Gerhold <stephan@gerhold.net> + +description: + This document describes the hardware for a component that loads and boots + firmware on the Qualcomm MSM8916 Modem Hexagon Core (and similar). + +properties: + compatible: + oneOf: + - enum: + - qcom,msm8909-mss-pil + - qcom,msm8916-mss-pil + - qcom,msm8953-mss-pil + - qcom,msm8974-mss-pil + + - const: qcom,q6v5-pil + description: Deprecated, prefer using qcom,msm8916-mss-pil + deprecated: true + + reg: + items: + - description: MSS QDSP6 registers + - description: RMB registers + + reg-names: + items: + - const: qdsp6 + - const: rmb + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + clocks: + items: + - description: Configuration interface (AXI) clock + - description: Configuration bus (AHB) clock + - description: Boot ROM (AHB) clock + - description: XO proxy clock (control handed over after startup) + + clock-names: + items: + - const: iface + - const: bus + - const: mem + - const: xo + + power-domains: + items: + - description: CX proxy power domain (control handed over after startup) + - description: MX proxy power domain (control handed over after startup) + - description: MSS proxy power domain (control handed over after startup) + (only valid for qcom,msm8953-mss-pil) + minItems: 2 + + power-domain-names: + items: + - const: cx + - const: mx + - const: mss # only valid for qcom,msm8953-mss-pil + minItems: 2 + + pll-supply: + description: PLL proxy supply (control handed over after startup) + + mss-supply: + description: MSS power domain supply (only valid for qcom,msm8974-mss-pil) + + resets: + items: + - description: MSS restart control + + reset-names: + items: + - const: mss_restart + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop modem + + qcom,smem-state-names: + description: Names of the states used by the AP to signal the Hexagon core + items: + - const: stop + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Halt registers are used to halt transactions of various sub-components + within MSS. + items: + - items: + - description: phandle to TCSR syscon region + - description: offset to the Q6 halt register + - description: offset to the modem halt register + - description: offset to the nc halt register + + memory-region: + items: + - description: MBA reserved region + - description: MPSS reserved region + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Name of MBA firmware + - description: Name of modem firmware + + bam-dmux: + $ref: /schemas/net/qcom,bam-dmux.yaml# + description: + Qualcomm BAM Data Multiplexer (provides network interface to the modem) + + smd-edge: + $ref: qcom,smd-edge.yaml# + description: + Qualcomm SMD subnode which represents communication edge, channels + and devices related to the DSP. + properties: + label: + enum: + - modem + - hexagon + unevaluatedProperties: false + + # Deprecated properties + cx-supply: + description: CX power domain regulator supply (prefer using power-domains) + deprecated: true + + mx-supply: + description: MX power domain regulator supply (prefer using power-domains) + deprecated: true + + mba: + type: object + description: + MBA reserved region (prefer using memory-region with two items) + properties: + memory-region: true + required: + - memory-region + deprecated: true + + mpss: + type: object + description: + MPSS reserved region (prefer using memory-region with two items) + properties: + memory-region: true + required: + - memory-region + deprecated: true + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - pll-supply + - resets + - reset-names + - qcom,halt-regs + - qcom,smem-states + - qcom,smem-state-names + - smd-edge + +allOf: + - if: + properties: + compatible: + const: qcom,msm8953-mss-pil + then: + properties: + power-domains: + minItems: 3 + power-domain-names: + minItems: 3 + required: + - power-domains + - power-domain-names + else: + properties: + power-domains: + maxItems: 2 + power-domain-names: + maxItems: 2 + + - if: + properties: + compatible: + const: qcom,msm8974-mss-pil + then: + required: + - mss-supply + else: + properties: + mss-supply: false + + # Fallbacks for deprecated properties + - oneOf: + - required: + - memory-region + - required: + - mba + - mpss + - oneOf: + - required: + - power-domains + - power-domain-names + - required: + - cx-supply + - mx-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8916.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,msm8916-mss-pil"; + reg = <0x04080000 0x100>, <0x04020000 0x40>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + qcom,smem-states = <&hexagon_smp2p_out 0>; + qcom,smem-state-names = "stop"; + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>; + clock-names = "iface", "bus", "mem", "xo"; + + power-domains = <&rpmpd MSM8916_VDDCX>, <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + pll-supply = <&pm8916_l7>; + + resets = <&scm 0>; + reset-names = "mss_restart"; + + memory-region = <&mba_mem>, <&mpss_mem>; + + smd-edge { + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + + qcom,smd-edge = <0>; + qcom,ipc = <&apcs 8 12>; + qcom,remote-pid = <1>; + + label = "hexagon"; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml new file mode 100644 index 000000000000..c1ac6ca1e759 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml @@ -0,0 +1,393 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,msm8996-mss-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8996 MSS Peripheral Image Loader (and similar) + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Sibi Sankar <quic_sibis@quicinc.com> + +description: + MSS Peripheral Image Loader loads and boots firmware on the + Qualcomm Technology Inc. MSM8996 Modem Hexagon Core (and similar). + +properties: + compatible: + enum: + - qcom,msm8996-mss-pil + - qcom,msm8998-mss-pil + - qcom,sdm845-mss-pil + + reg: + items: + - description: MSS QDSP6 registers + - description: RMB registers + + reg-names: + items: + - const: qdsp6 + - const: rmb + + iommus: + items: + - description: MSA Stream 1 + - description: MSA Stream 2 + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + clocks: + minItems: 8 + maxItems: 9 + + clock-names: + minItems: 8 + maxItems: 9 + + power-domains: + items: + - description: CX power domain + - description: MX power domain + - description: MSS power domain (only valid for qcom,sdm845-mss-pil) + minItems: 2 + + power-domain-names: + items: + - const: cx + - const: mx + - const: mss # only valid for qcom,sdm845-mss-pil + minItems: 2 + + pll-supply: + description: PLL supply + + resets: + items: + - description: AOSS restart + - description: PDC reset (only valid for qcom,sdm845-mss-pil) + minItems: 1 + + reset-names: + items: + - const: mss_restart + - const: pdc_reset # only valid for qcom,sdm845-mss-pil + minItems: 1 + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop modem + + qcom,smem-state-names: + description: Names of the states used by the AP to signal the Hexagon core + items: + - const: stop + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Halt registers are used to halt transactions of various sub-components + within MSS. + items: + - items: + - description: phandle to TCSR syscon region + - description: offset to the Q6 halt register + - description: offset to the modem halt register + - description: offset to the nc halt register + + memory-region: + items: + - description: MBA reserved region + - description: Modem reserved region + - description: Metadata reserved region + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Name of MBA firmware + - description: Name of modem firmware + + smd-edge: + $ref: /schemas/remoteproc/qcom,smd-edge.yaml# + description: + Qualcomm Shared Memory subnode which represents communication edge, + channels and devices related to the Modem. + unevaluatedProperties: false + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the Modem. + unevaluatedProperties: false + + # Deprecated properties + mba: + type: object + description: + MBA reserved region + + properties: + memory-region: true + + required: + - memory-region + + additionalProperties: false + deprecated: true + + mpss: + type: object + description: + MPSS reserved region + + properties: + memory-region: true + + required: + - memory-region + + additionalProperties: false + deprecated: true + + metadata: + type: object + description: + Metadata reserved region + + properties: + memory-region: true + + required: + - memory-region + + additionalProperties: false + deprecated: true + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - qcom,halt-regs + - qcom,smem-states + - qcom,smem-state-names + +allOf: + - if: + properties: + compatible: + const: qcom,msm8996-mss-pil + then: + properties: + clocks: + items: + - description: GCC MSS IFACE clock + - description: GCC MSS BUS clock + - description: GCC MSS MEM clock + - description: RPMH XO clock + - description: GCC MSS GPLL0 clock + - description: GCC MSS SNOC_AXI clock + - description: GCC MSS MNOC_AXI clock + - description: RPMH PNOC clock + - description: GCC MSS PRNG clock + - description: RPMH QDSS clock + clock-names: + items: + - const: iface + - const: bus + - const: mem + - const: xo + - const: gpll0_mss + - const: snoc_axi + - const: mnoc_axi + - const: pnoc + - const: qdss + glink-edge: false + required: + - pll-supply + - smd-edge + else: + properties: + pll-supply: false + smd-edge: false + + - if: + properties: + compatible: + const: qcom,msm8998-mss-pil + then: + properties: + clocks: + items: + - description: GCC MSS IFACE clock + - description: GCC MSS BUS clock + - description: GCC MSS MEM clock + - description: GCC MSS GPLL0 clock + - description: GCC MSS SNOC_AXI clock + - description: GCC MSS MNOC_AXI clock + - description: RPMH QDSS clock + - description: RPMH XO clock + clock-names: + items: + - const: iface + - const: bus + - const: mem + - const: gpll0_mss + - const: snoc_axi + - const: mnoc_axi + - const: qdss + - const: xo + required: + - glink-edge + + - if: + properties: + compatible: + const: qcom,sdm845-mss-pil + then: + properties: + power-domains: + minItems: 3 + power-domain-names: + minItems: 3 + resets: + minItems: 2 + reset-names: + minItems: 2 + clocks: + items: + - description: GCC MSS IFACE clock + - description: GCC MSS BUS clock + - description: GCC MSS MEM clock + - description: GCC MSS GPLL0 clock + - description: GCC MSS SNOC_AXI clock + - description: GCC MSS MNOC_AXI clock + - description: GCC MSS PRNG clock + - description: RPMH XO clock + clock-names: + items: + - const: iface + - const: bus + - const: mem + - const: gpll0_mss + - const: snoc_axi + - const: mnoc_axi + - const: prng + - const: xo + required: + - qcom,qmp + - glink-edge + else: + properties: + iommus: false + power-domains: + maxItems: 2 + power-domain-names: + maxItems: 2 + resets: + maxItems: 1 + reset-names: + maxItems: 1 + qcom,qmp: false + + # Fallbacks for deprecated properties + - oneOf: + - required: + - memory-region + - required: + - mba + - mpss + - metadata + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/reset/qcom,sdm845-aoss.h> + #include <dt-bindings/reset/qcom,sdm845-pdc.h> + + remoteproc@4080000 { + compatible = "qcom,sdm845-mss-pil"; + reg = <0x04080000 0x408>, <0x04180000 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&gcc GCC_PRNG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "prng", "xo"; + + power-domains = <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>, + <&rpmhpd SDM845_MSS>; + power-domain-names = "cx", "mx", "mss"; + + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml new file mode 100644 index 000000000000..171ef85de193 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,pas-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Peripheral Authentication Service Common Properties + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Common properties of Qualcomm SoCs Peripheral Authentication Service. + +properties: + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + + interconnects: + maxItems: 1 + + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + power-domains: + minItems: 1 + maxItems: 3 + + power-domain-names: + minItems: 1 + maxItems: 3 + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop the modem + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output + items: + - const: stop + + smd-edge: + $ref: /schemas/remoteproc/qcom,smd-edge.yaml# + description: + Qualcomm Shared Memory subnode which represents communication edge, + channels and devices related to the ADSP. + unevaluatedProperties: false + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the ADSP. + unevaluatedProperties: false + +required: + - clocks + - clock-names + - interrupts + - interrupt-names + - memory-region + - qcom,smem-states + - qcom,smem-state-names + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index d0ebd16ee0e1..573a88b60677 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -7,14 +7,8 @@ on the Qualcomm Hexagon core. Usage: required Value type: <string> Definition: must be one of: - "qcom,q6v5-pil", "qcom,ipq8074-wcss-pil" "qcom,qcs404-wcss-pil" - "qcom,msm8916-mss-pil", - "qcom,msm8974-mss-pil" - "qcom,msm8996-mss-pil" - "qcom,msm8998-mss-pil" - "qcom,sdm845-mss-pil" - reg: Usage: required @@ -35,26 +29,7 @@ on the Qualcomm Hexagon core. - interrupt-names: Usage: required Value type: <stringlist> - Definition: The interrupts needed depends on the compatible - string: - qcom,q6v5-pil: - qcom,ipq8074-wcss-pil: - qcom,qcs404-wcss-pil: - qcom,msm8916-mss-pil: - qcom,msm8974-mss-pil: - must be "wdog", "fatal", "ready", "handover", "stop-ack" - qcom,msm8996-mss-pil: - qcom,msm8998-mss-pil: - qcom,sdm845-mss-pil: - must be "wdog", "fatal", "ready", "handover", "stop-ack", - "shutdown-ack" - -- firmware-name: - Usage: optional - Value type: <stringlist> - Definition: must list the relative firmware image paths for mba and - modem. They are used for booting and authenticating the - Hexagon core. + Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack" - clocks: Usage: required @@ -72,67 +47,23 @@ on the Qualcomm Hexagon core. "gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc", "lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc", "lcc_axim_cbc", "lcc_bcr_sleep" - qcom,q6v5-pil: - qcom,msm8916-mss-pil: - qcom,msm8974-mss-pil: - must be "iface", "bus", "mem", "xo" - qcom,msm8996-mss-pil: - must be "iface", "bus", "mem", "xo", "gpll0_mss", - "snoc_axi", "mnoc_axi", "pnoc", "qdss" - qcom,msm8998-mss-pil: - must be "iface", "bus", "mem", "xo", "gpll0_mss", - "snoc_axi", "mnoc_axi", "qdss" - qcom,sdm845-mss-pil: - must be "iface", "bus", "mem", "xo", "gpll0_mss", - "snoc_axi", "mnoc_axi", "prng" - resets: Usage: required Value type: <phandle> - Definition: reference to the reset-controller for the modem sub-system - reference to the list of 3 reset-controllers for the + Definition: reference to the list of 3 reset-controllers for the wcss sub-system - reference to the list of 2 reset-controllers for the modem - sub-system on SDM845 SoCs - reset-names: Usage: required Value type: <stringlist> - Definition: must be "mss_restart" for the modem sub-system - must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" + Definition: must be "wcss_aon_reset", "wcss_reset", "wcss_q6_reset" for the wcss sub-system - must be "mss_restart", "pdc_reset" for the modem - sub-system on SDM845 SoCs -For devices where the mba and mpss sub-nodes are not specified, mba/mpss region -should be referenced as follows: - memory-region: Usage: required Value type: <phandle> - Definition: reference to the reserved-memory for the mba region followed - by the mpss region - -For the compatible strings below the following supplies are required: - "qcom,q6v5-pil" - "qcom,msm8916-mss-pil", -- cx-supply: (deprecated, use power domain instead) -- mx-supply: (deprecated, use power domain instead) -- pll-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the Hexagon core - -For the compatible string below the following supplies are required: - "qcom,msm8974-mss-pil" -- cx-supply: (deprecated, use power domain instead) -- mss-supply: -- mx-supply: (deprecated, use power domain instead) -- pll-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the Hexagon core + Definition: reference to wcss reserved-memory region. For the compatible string below the following supplies are required: "qcom,qcs404-wcss-pil" @@ -142,39 +73,6 @@ For the compatible string below the following supplies are required: Definition: reference to the regulators to be held on behalf of the booting of the Hexagon core -For the compatible string below the following supplies are required: - "qcom,msm8996-mss-pil" -- pll-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the Hexagon core - -- power-domains: - Usage: required - Value type: <phandle> - Definition: reference to power-domains that match power-domain-names - -- power-domain-names: - Usage: required - Value type: <stringlist> - Definition: The power-domains needed depend on the compatible string: - qcom,ipq8074-wcss-pil: - no power-domain names required - qcom,q6v5-pil: - qcom,msm8916-mss-pil: - qcom,msm8974-mss-pil: - qcom,msm8996-mss-pil: - qcom,msm8998-mss-pil: - must be "cx", "mx" - qcom,sdm845-mss-pil: - must be "cx", "mx", "mss" - -- qcom,qmp: - Usage: optional - Value type: <phandle> - Definition: reference to the AOSS side-channel message RAM. - - qcom,smem-states: Usage: required Value type: <phandle> @@ -190,16 +88,9 @@ For the compatible string below the following supplies are required: Usage: required Value type: <prop-encoded-array> Definition: a phandle reference to a syscon representing TCSR followed - by the three offsets within syscon for q6, modem and nc + by the three offsets within syscon for q6, wcss and nc halt registers. -The Hexagon node must contain iommus property as described in ../iommu/iommu.txt -on platforms which do not have TrustZone. - -= SUBNODES: -The Hexagon node must contain two subnodes, named "mba" and "mpss" representing -the memory regions used by the Hexagon firmware. Each sub-node must contain: - - memory-region: Usage: required Value type: <phandle> @@ -209,56 +100,3 @@ The Hexagon node may also have an subnode named either "smd-edge" or "glink-edge" that describes the communication edge, channels and devices related to the Hexagon. See ../soc/qcom/qcom,smd.yaml and ../soc/qcom/qcom,glink.txt for details on how to describe these. - -= EXAMPLE -The following example describes the resources needed to boot control the -Hexagon, as it is found on MSM8974 boards. - - remoteproc@fc880000 { - compatible = "qcom,msm8974-mss-pil"; - reg = <0xfc880000 0x100>, <0xfc820000 0x020>; - reg-names = "qdsp6", "rmb"; - - interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, - <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, - <&gcc GCC_MSS_CFG_AHB_CLK>, - <&gcc GCC_BOOT_ROM_AHB_CLK>, - <&xo_board>; - clock-names = "iface", "bus", "mem", "xo"; - - resets = <&gcc GCC_MSS_RESTART>; - reset-names = "mss_restart"; - - cx-supply = <&pm8841_s2>; - mss-supply = <&pm8841_s3>; - mx-supply = <&pm8841_s1>; - pll-supply = <&pm8941_l12>; - - qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>; - - qcom,smem-states = <&modem_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - mba { - memory-region = <&mba_region>; - }; - - mpss { - memory-region = <&mpss_region>; - }; - - smd-edge { - interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&apcs 8 12>; - qcom,smd-edge = <0>; - - label = "modem"; - }; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml new file mode 100644 index 000000000000..5efa0e5c0439 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS404 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm QCS404 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,qcs404-adsp-pas + - qcom,qcs404-cdsp-pas + - qcom,qcs404-wcss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + interrupts: + maxItems: 5 + + interrupt-names: + maxItems: 5 + + power-domains: false + power-domain-names: false + smd-edge: false + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + remoteproc@c700000 { + compatible = "qcom,qcs404-adsp-pas"; + reg = <0x0c700000 0x4040>; + + clocks = <&xo_board>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_fw_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; + + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + label = "adsp"; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml index e4a7da8020f4..b1402bef0ebe 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml @@ -95,6 +95,7 @@ properties: items: - description: MBA reserved region - description: modem reserved region + - description: metadata reserved region firmware-name: $ref: /schemas/types.yaml#/definitions/string-array @@ -223,7 +224,7 @@ examples: <&rpmhpd SC7180_MSS>; power-domain-names = "cx", "mx", "mss"; - memory-region = <&mba_mem>, <&mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; qcom,qmp = <&aoss_qmp>; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml new file mode 100644 index 000000000000..5cefd2c58593 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7180/SC7280 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC7180/SC7280 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sc7180-mpss-pas + - qcom,sc7280-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + interrupts: + minItems: 6 + + interrupt-names: + minItems: 6 + + power-domains: + minItems: 2 + items: + - description: CX power domain + - description: MX power domain + - description: MSS power domain + + power-domain-names: + minItems: 2 + items: + - const: cx + - const: mx + - const: mss + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sc7180-mpss-pas + then: + properties: + power-domains: + minItems: 3 + power-domain-names: + minItems: 3 + else: + properties: + power-domains: + maxItems: 2 + power-domain-names: + maxItems: 2 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@4080000 { + compatible = "qcom,sc7180-mpss-pas"; + reg = <0x04080000 0x4040>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + memory-region = <&mpss_mem>; + + power-domains = <&rpmhpd SC7180_CX>, + <&rpmhpd SC7180_MX>, + <&rpmhpd SC7180_MSS>; + power-domain-names = "cx", "mx", "mss"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml new file mode 100644 index 000000000000..94ca7a0cc203 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-adsp-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 ADSP Peripheral Image Loader + +maintainers: + - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> + +description: + This document describes the hardware for a component that loads and boots firmware + on the Qualcomm Technology Inc. ADSP. + +properties: + compatible: + enum: + - qcom,sc7280-adsp-pil + + reg: + items: + - description: qdsp6ss register + - description: efuse q6ss register + + iommus: + items: + - description: Phandle to apps_smmu node with sid mask + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + clocks: + items: + - description: XO clock + - description: GCC CFG NOC LPASS clock + + clock-names: + items: + - const: xo + - const: gcc_cfg_noc_lpass + + power-domains: + items: + - description: LCX power domain + + resets: + items: + - description: PDC AUDIO SYNC RESET + - description: CC LPASS restart + + reset-names: + items: + - const: pdc_sync + - const: cc_lpass + + memory-region: + maxItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle reference to a syscon representing TCSR followed by the + four offsets within syscon for q6, modem, nc and qv6 halt registers. + items: + - items: + - description: phandle to TCSR_MUTEX registers + - description: offset to the Q6 halt register + - description: offset to the modem halt register + - description: offset to the nc halt register + - description: offset to the vq6 halt register + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop the modem + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output + const: stop + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + glink-edge: + $ref: qcom,glink-edge.yaml# + type: object + unevaluatedProperties: false + description: | + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the ADSP. + + properties: + label: + const: lpass + + gpr: true + apr: false + fastrpc: false + + required: + - label + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - reset-names + - qcom,halt-regs + - memory-region + - qcom,smem-states + - qcom,smem-state-names + - qcom,qmp + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,lpass-sc7280.h> + #include <dt-bindings/reset/qcom,sdm845-aoss.h> + #include <dt-bindings/reset/qcom,sdm845-pdc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + + remoteproc@3000000 { + compatible = "qcom,sc7280-adsp-pil"; + reg = <0x03000000 0x5000>, + <0x0355b000 0x10>; + + interrupts-extended = <&pdc 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CFG_NOC_LPASS_CLK>; + clock-names = "xo", "gcc_cfg_noc_lpass"; + + power-domains = <&rpmhpd SC7280_LCX>; + + resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>, + <&aoss_reset AOSS_CC_LPASS_RESTART>; + reset-names = "pdc_sync", "cc_lpass"; + + qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; + + memory-region = <&adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + qcom,qmp = <&aoss_qmp>; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml index b4de0521a89d..005cb21732af 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml @@ -95,6 +95,7 @@ properties: items: - description: MBA reserved region - description: modem reserved region + - description: metadata reserved region firmware-name: $ref: /schemas/types.yaml#/definitions/string-array @@ -240,7 +241,7 @@ examples: <&rpmhpd SC7280_MSS>; power-domain-names = "cx", "mss"; - memory-region = <&mba_mem>, <&mpss_mem>; + memory-region = <&mba_mem>, <&mpss_mem>, <&mdata_mem>; qcom,qmp = <&aoss_qmp>; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml new file mode 100644 index 000000000000..c1f8dd8d0e4c --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8180x-pas.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc8180x-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180X Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC8180X SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + - qcom,sc8180x-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + else: + properties: + # TODO: incomplete + power-domains: false + power-domain-names: false + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml new file mode 100644 index 000000000000..f6fbc531dc28 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SC8280XP SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sc8280xp-adsp-pas + - qcom,sc8280xp-nsp0-pas + - qcom,sc8280xp-nsp1-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sc8280xp-nsp0-pas + - qcom,sc8280xp-nsp1-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sc8280xp-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + else: + properties: + power-domains: + items: + - description: NSP power domain + power-domain-names: + items: + - const: nsp + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@3000000 { + compatible = "qcom,sc8280xp-adsp-pas"; + reg = <0x03000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + firmware-name = "qcom/sc8280xp/qcadsp8280.mbn"; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + memory-region = <&pil_adsp_mem>; + + power-domains = <&rpmhpd SC8280XP_LCX>, + <&rpmhpd SC8280XP_LMX>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml new file mode 100644 index 000000000000..c66e298462c7 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sdx55-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDX55 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SDX55 SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sdx55-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + interrupts: + minItems: 6 + + interrupt-names: + minItems: 6 + + power-domains: + items: + - description: CX power domain + - description: MSS power domain + + power-domain-names: + items: + - const: cx + - const: mss + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@4080000 { + compatible = "qcom,sdx55-mpss-pas"; + reg = <0x04080000 0x4040>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + memory-region = <&mpss_adsp_mem>; + + power-domains = <&rpmhpd SDX55_CX>, <&rpmhpd SDX55_MSS>; + power-domain-names = "cx", "mss"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; + label = "mpss"; + mboxes = <&apcs 15>; + qcom,remote-pid = <1>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml new file mode 100644 index 000000000000..f5d1fa9f45f1 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm6115-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 Peripheral Authentication Service + +maintainers: + - Bhupesh Sharma <bhupesh.sharma@linaro.org> + +description: + Qualcomm SM6115 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm6115-adsp-pas + - qcom,sm6115-cdsp-pas + - qcom,sm6115-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm6115-adsp-pas + - qcom,sm6115-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sm6115-cdsp-pas + - qcom,sm6115-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + power-domain-names: + items: + - const: cx + + - if: + properties: + compatible: + enum: + - qcom,sm6115-adsp-pas + then: + properties: + power-domains: + items: + - description: LPI CX power domain + - description: LPI MX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@ab00000 { + compatible = "qcom,sm6115-adsp-pas"; + reg = <0x0ab00000 0x100>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + firmware-name = "qcom/sm6115/adsp.mdt"; + + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&pil_adsp_mem>; + + power-domains = <&rpmpd SM6115_VDD_LPI_CX>, + <&rpmpd SM6115_VDD_LPI_MX>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + /* ... */ + + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml new file mode 100644 index 000000000000..fee02fa800b5 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm6350-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM6350 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm6350-adsp-pas + - qcom,sm6350-cdsp-pas + - qcom,sm6350-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm6350-adsp-pas + - qcom,sm6350-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sm6350-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,sm6350-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MX power domain + power-domain-names: + items: + - const: cx + - const: mx + + - if: + properties: + compatible: + enum: + - qcom,sm6350-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@3000000 { + compatible = "qcom,sm6350-adsp-pas"; + reg = <0x03000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&pil_adsp_mem>; + + power-domains = <&rpmhpd SM6350_LCX>, + <&rpmhpd SM6350_LMX>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml new file mode 100644 index 000000000000..2c085ac2c3fb --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm8150-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150/SM8250 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8150/SM8250 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm8150-adsp-pas + - qcom,sm8150-cdsp-pas + - qcom,sm8150-mpss-pas + - qcom,sm8150-slpi-pas + - qcom,sm8250-adsp-pas + - qcom,sm8250-cdsp-pas + - qcom,sm8250-slpi-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8150-adsp-pas + - qcom,sm8150-cdsp-pas + - qcom,sm8150-slpi-pas + - qcom,sm8250-adsp-pas + - qcom,sm8250-cdsp-pas + - qcom,sm8250-slpi-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sm8150-adsp-pas + - qcom,sm8150-cdsp-pas + - qcom,sm8250-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + power-domain-names: + items: + - const: cx + + - if: + properties: + compatible: + enum: + - qcom,sm8150-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + + - if: + properties: + compatible: + enum: + - qcom,sm8150-slpi-pas + - qcom,sm8250-adsp-pas + - qcom,sm8250-slpi-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@17300000 { + compatible = "qcom,sm8150-adsp-pas"; + reg = <0x17300000 0x4040>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + firmware-name = "qcom/sm8150/adsp.mbn"; + + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_mem>; + + power-domains = <&rpmhpd SM8150_CX>; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apss_shared 8>; + + /* ... */ + + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml new file mode 100644 index 000000000000..af24f9a3cdf1 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm8350-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350/SM8450 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8350/SM8450 SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm8350-adsp-pas + - qcom,sm8350-cdsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8350-mpss-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-mpss-pas + - qcom,sm8450-slpi-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + memory-region: + minItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: Firmware name for the Hexagon core + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8350-adsp-pas + - qcom,sm8350-cdsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-slpi-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + + - if: + properties: + compatible: + enum: + - qcom,sm8350-mpss-pas + - qcom,sm8450-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + + - if: + properties: + compatible: + enum: + - qcom,sm8350-adsp-pas + - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-slpi-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,sm8350-cdsp-pas + - qcom,sm8450-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MXC power domain + power-domain-names: + items: + - const: cx + - const: mxc + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@30000000 { + compatible = "qcom,sm8450-adsp-pas"; + reg = <0x030000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + firmware-name = "qcom/sm8450/adsp.mbn"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_mem>; + + power-domains = <&rpmhpd SM8450_LCX>, + <&rpmhpd SM8450_LMX>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml new file mode 100644 index 000000000000..fe216aa531ed --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sm8550-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Peripheral Authentication Service + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: + Qualcomm SM8550 SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + - qcom,sm8550-cdsp-pas + - qcom,sm8550-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + memory-region: + minItems: 2 + items: + - description: Memory region for main Firmware authentication + - description: Memory region for Devicetree Firmware authentication + - description: DSM Memory region + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + - qcom,sm8550-cdsp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + maxItems: 2 + else: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + minItems: 3 + + - if: + properties: + compatible: + enum: + - qcom,sm8550-adsp-pas + then: + properties: + power-domains: + items: + - description: LCX power domain + - description: LMX power domain + power-domain-names: + items: + - const: lcx + - const: lmx + + - if: + properties: + compatible: + enum: + - qcom,sm8550-mpss-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MSS power domain + power-domain-names: + items: + - const: cx + - const: mss + - if: + properties: + compatible: + enum: + - qcom,sm8550-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MXC power domain + - description: NSP power domain + power-domain-names: + items: + - const: cx + - const: mxc + - const: nsp + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + + remoteproc@30000000 { + compatible = "qcom,sm8550-adsp-pas"; + reg = <0x030000000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + memory-region = <&adsp_mem>, <&dtb_adsp_mem>; + + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + + power-domains = <&rpmhpd_sm8550_lcx>, + <&rpmhpd_sm8550_lmx>; + power-domain-names = "lcx", "lmx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt deleted file mode 100644 index ac423f4c3f1b..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt +++ /dev/null @@ -1,177 +0,0 @@ -Qualcomm WCNSS Peripheral Image Loader - -This document defines the binding for a component that loads and boots firmware -on the Qualcomm WCNSS core. - -- compatible: - Usage: required - Value type: <string> - Definition: must be one of: - "qcom,riva-pil", - "qcom,pronto-v1-pil", - "qcom,pronto-v2-pil" - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: must specify the base address and size of the CCU, DXE and - PMU register blocks - -- reg-names: - Usage: required - Value type: <stringlist> - Definition: must be "ccu", "dxe", "pmu" - -- interrupts-extended: - Usage: required - Value type: <prop-encoded-array> - Definition: must list the watchdog and fatal IRQs and may specify the - ready, handover and stop-ack IRQs - -- interrupt-names: - Usage: required - Value type: <stringlist> - Definition: should be "wdog", "fatal", optionally followed by "ready", - "handover", "stop-ack" - -- firmware-name: - Usage: optional - Value type: <string> - Definition: must list the relative firmware image path for the - WCNSS core. Defaults to "wcnss.mdt". - -- vddmx-supply: (deprecated for qcom,pronto-v1/2-pil) -- vddcx-supply: (deprecated for qcom,pronto-v1/2-pil) -- vddpx-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the WCNSS core - -- power-domains: - Usage: required (for qcom,pronto-v1/2-pil) - Value type: <phandle> - Definition: reference to the power domains to be held on behalf of the - booting of the WCNSS core - -- power-domain-names: - Usage: required (for qcom,pronto-v1/2-pil) - Value type: <stringlist> - Definition: must be "cx", "mx" - -- qcom,smem-states: - Usage: optional - Value type: <prop-encoded-array> - Definition: reference to the SMEM state used to indicate to WCNSS that - it should shut down - -- qcom,smem-state-names: - Usage: optional - Value type: <stringlist> - Definition: should be "stop" - -- memory-region: - Usage: required - Value type: <prop-encoded-array> - Definition: reference to reserved-memory node for the remote processor - see ../reserved-memory/reserved-memory.txt - -= SUBNODES -A required subnode of the WCNSS PIL is used to describe the attached rf module -and its resource dependencies. It is described by the following properties: - -- compatible: - Usage: required - Value type: <string> - Definition: must be one of: - "qcom,wcn3620", - "qcom,wcn3660", - "qcom,wcn3660b", - "qcom,wcn3680" - -- clocks: - Usage: required - Value type: <prop-encoded-array> - Definition: should specify the xo clock and optionally the rf clock - -- clock-names: - Usage: required - Value type: <stringlist> - Definition: should be "xo", optionally followed by "rf" - -- vddxo-supply: -- vddrfa-supply: -- vddpa-supply: -- vdddig-supply: - Usage: required - Value type: <phandle> - Definition: reference to the regulators to be held on behalf of the - booting of the WCNSS core - - -The wcnss node can also have an subnode named "smd-edge" that describes the SMD -edge, channels and devices related to the WCNSS. -See ../soc/qcom/qcom,smd.yaml for details on how to describe the SMD edge. - -= EXAMPLE -The following example describes the resources needed to boot control the WCNSS, -with attached WCN3680, as it is commonly found on MSM8974 boards. - -pronto@fb204000 { - compatible = "qcom,pronto-v2-pil"; - reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - - interrupts-extended = <&intc 0 149 1>, - <&wcnss_smp2p_slave 0 0>, - <&wcnss_smp2p_slave 1 0>, - <&wcnss_smp2p_slave 2 0>, - <&wcnss_smp2p_slave 3 0>; - interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - - power-domains = <&rpmpd MSM8974_VDDCX>, <&rpmpd MSM8974_VDDMX>; - power-domain-names = "cx", "mx"; - - vddpx-supply = <&pm8941_s3>; - - qcom,smem-states = <&wcnss_smp2p_out 0>; - qcom,smem-state-names = "stop"; - - memory-region = <&wcnss_region>; - - pinctrl-names = "default"; - pinctrl-0 = <&wcnss_pin_a>; - - iris { - compatible = "qcom,wcn3680"; - - clocks = <&rpmcc RPM_CXO_CLK_SRC>, <&rpmcc RPM_CXO_A2>; - clock-names = "xo", "rf"; - - vddxo-supply = <&pm8941_l6>; - vddrfa-supply = <&pm8941_l11>; - vddpa-supply = <&pm8941_l19>; - vdddig-supply = <&pm8941_s3>; - }; - - smd-edge { - interrupts = <0 142 1>; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - qcom,remote-pid = <4>; - - label = "pronto"; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml new file mode 100644 index 000000000000..45eb42bd3c2c --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml @@ -0,0 +1,294 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,wcnss-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm WCNSS Peripheral Image Loader + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + This document defines the binding for a component that loads and boots + firmware on the Qualcomm WCNSS core. + +properties: + compatible: + description: + Append "qcom,pronto" if the device is actually pronto, and not riva + oneOf: + - items: + - enum: + - qcom,pronto-v1-pil + - qcom,pronto-v2-pil + - qcom,pronto-v3-pil + - const: qcom,pronto + - const: qcom,riva-pil + + reg: + maxItems: 3 + description: + The base address and size of the CCU, DXE and PMU register blocks + + reg-names: + items: + - const: ccu + - const: dxe + - const: pmu + + interrupts: + minItems: 2 + maxItems: 5 + + interrupt-names: + minItems: 2 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Relative firmware image path for the WCNSS core. Defaults to + "wcnss.mdt". + + vddpx-supply: + description: + PX regulator to be held on behalf of the booting of the WCNSS core + + vddmx-supply: + description: + MX regulator to be held on behalf of the booting of the WCNSS core. + + vddcx-supply: + description: + CX regulator to be held on behalf of the booting of the WCNSS core. + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: cx + - const: mx + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + States used by the AP to signal the WCNSS core that it should shutdown + items: + - description: Stop the modem + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output + items: + - const: stop + + memory-region: + maxItems: 1 + description: reserved-memory for the WCNSS core + + smd-edge: + $ref: /schemas/remoteproc/qcom,smd-edge.yaml# + description: + Qualcomm Shared Memory subnode which represents communication edge, + channels and devices related to the ADSP. + + iris: + type: object + description: + The iris subnode of the WCNSS PIL is used to describe the attached RF module + and its resource dependencies. + + properties: + compatible: + enum: + - qcom,wcn3620 + - qcom,wcn3660 + - qcom,wcn3660b + - qcom,wcn3680 + + clocks: + minItems: 1 + items: + - description: XO clock + - description: RF clock + + clock-names: + minItems: 1 + items: + - const: xo + - const: rf + + vddxo-supply: + description: + Reference to the regulator to be held on behalf of the booting WCNSS + core + + vddrfa-supply: + description: + Reference to the regulator to be held on behalf of the booting WCNSS + core + + vddpa-supply: + description: + Reference to the regulator to be held on behalf of the booting WCNSS + core + + vdddig-supply: + description: + Reference to the regulator to be held on behalf of the booting WCNSS + core + + required: + - compatible + - clocks + - clock-names + - vddxo-supply + - vddrfa-supply + - vddpa-supply + - vdddig-supply + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - iris + - vddpx-supply + - memory-region + - smd-edge + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,riva-pil + then: + required: + - vddcx-supply + - vddmx-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,pronto-v1-pil + - qcom,pronto-v2-pil + then: + properties: + vddmx-supply: + deprecated: true + description: Deprecated for qcom,pronto-v1/2-pil + + vddcx-supply: + deprecated: true + description: Deprecated for qcom,pronto-v1/2-pil + + oneOf: + - required: + - power-domains + - power-domain-names + - required: + - vddmx-supply + - vddcx-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,pronto-v3-pil + then: + properties: + vddmx-supply: false + vddcx-supply: false + + required: + - power-domains + - power-domain-names + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + pronto@a21b000 { + compatible = "qcom,pronto-v2-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8916_VDDCX>, <&rpmpd MSM8916_VDDMX>; + power-domain-names = "cx", "mx"; + + vddpx-supply = <&pm8916_l7>; + + qcom,smem-states = <&wcnss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + memory-region = <&wcnss_region>; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + iris { + compatible = "qcom,wcn3620"; + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; + + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&pronto>; + + bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml index cedbc5efdc56..f16e90380df1 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml @@ -31,10 +31,12 @@ allOf: properties: compatible: enum: + - ti,am62a-c7xv-dsp - ti,j721e-c66-dsp - ti,j721e-c71-dsp - ti,j721s2-c71-dsp description: + Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs @@ -109,6 +111,7 @@ else: properties: compatible: enum: + - ti,am62a-c7xv-dsp - ti,j721e-c71-dsp - ti,j721s2-c71-dsp then: diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml b/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml new file mode 100644 index 000000000000..c6d86964b72a --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,pru-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common TI PRU Consumer Binding + +maintainers: + - Suman Anna <s-anna@ti.com> + +description: | + A PRU application/consumer/user node typically uses one or more PRU device + nodes to implement a PRU application/functionality. Each application/client + node would need a reference to at least a PRU node, and optionally define + some properties needed for hardware/firmware configuration. The below + properties are a list of common properties supported by the PRU remoteproc + infrastructure. + + The application nodes shall define their own bindings like regular platform + devices, so below are in addition to each node's bindings. + +properties: + ti,prus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: phandles to the PRU, RTU or Tx_PRU nodes used + minItems: 1 + maxItems: 6 + items: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string-array + minItems: 1 + maxItems: 6 + description: | + firmwares for the PRU cores, the default firmware for the core from + the PRU node will be used if not provided. The firmware names should + correspond to the PRU cores listed in the 'ti,prus' property + + ti,pruss-gp-mux-sel: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 6 + items: + enum: [0, 1, 2, 3, 4] + description: | + array of values for the GP_MUX_SEL under PRUSS_GPCFG register for a PRU. + This selects the internal muxing scheme for the PRU instance. Values + should correspond to the PRU cores listed in the 'ti,prus' property. The + GP_MUX_SEL setting is a per-slice setting (one setting for PRU0, RTU0, + and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the + same slice in the associative array. If the array size is smaller than + the size of 'ti,prus' property, the default out-of-reset value (0) for the + PRU core is used. + +required: + - ti,prus + +additionalProperties: true diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d421a2ccaa1e..0861b76f185f 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -649,6 +649,7 @@ static const struct rproc_ops scp_ops = { .load = scp_load, .da_to_va = scp_da_to_va, .parse_fw = scp_parse_fw, + .sanity_check = rproc_elf_sanity_check, }; /** diff --git a/drivers/remoteproc/mtk_scp_ipi.c b/drivers/remoteproc/mtk_scp_ipi.c index 00f041ebcde6..fc55df649b40 100644 --- a/drivers/remoteproc/mtk_scp_ipi.c +++ b/drivers/remoteproc/mtk_scp_ipi.c @@ -6,13 +6,17 @@ #include <linux/clk.h> #include <linux/err.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/time64.h> #include <linux/remoteproc/mtk_scp.h> #include "mtk_common.h" +#define SCP_TIMEOUT_US (2000 * USEC_PER_MSEC) + /** * scp_ipi_register() - register an ipi function * @@ -156,7 +160,7 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len, unsigned int wait) { struct mtk_share_obj __iomem *send_obj = scp->send_buf; - unsigned long timeout; + u32 val; int ret; if (WARN_ON(id <= SCP_IPI_INIT) || WARN_ON(id >= SCP_IPI_MAX) || @@ -164,23 +168,21 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len, WARN_ON(len > sizeof(send_obj->share_buf)) || WARN_ON(!buf)) return -EINVAL; - mutex_lock(&scp->send_lock); - ret = clk_prepare_enable(scp->clk); if (ret) { dev_err(scp->dev, "failed to enable clock\n"); - goto unlock_mutex; + return ret; } + mutex_lock(&scp->send_lock); + /* Wait until SCP receives the last command */ - timeout = jiffies + msecs_to_jiffies(2000); - do { - if (time_after(jiffies, timeout)) { - dev_err(scp->dev, "%s: IPI timeout!\n", __func__); - ret = -ETIMEDOUT; - goto clock_disable; - } - } while (readl(scp->reg_base + scp->data->host_to_scp_reg)); + ret = readl_poll_timeout_atomic(scp->reg_base + scp->data->host_to_scp_reg, + val, !val, 0, SCP_TIMEOUT_US); + if (ret) { + dev_err(scp->dev, "%s: IPI timeout!\n", __func__); + goto unlock_mutex; + } scp_memcpy_aligned(send_obj->share_buf, buf, len); @@ -194,10 +196,9 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len, if (wait) { /* wait for SCP's ACK */ - timeout = msecs_to_jiffies(wait); ret = wait_event_timeout(scp->ack_wq, scp->ipi_id_ack[id], - timeout); + msecs_to_jiffies(wait)); scp->ipi_id_ack[id] = false; if (WARN(!ret, "scp ipi %d ack time out !", id)) ret = -EIO; @@ -205,10 +206,9 @@ int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len, ret = 0; } -clock_disable: - clk_disable_unprepare(scp->clk); unlock_mutex: mutex_unlock(&scp->send_lock); + clk_disable_unprepare(scp->clk); return ret; } diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c index 128bf9912f2c..b76db7fa693d 100644 --- a/drivers/remoteproc/pru_rproc.c +++ b/drivers/remoteproc/pru_rproc.c @@ -2,12 +2,14 @@ /* * PRU-ICSS remoteproc driver for various TI SoCs * - * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2014-2022 Texas Instruments Incorporated - https://www.ti.com/ * * Author(s): * Suman Anna <s-anna@ti.com> * Andrew F. Davis <afd@ti.com> * Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments + * Puranjay Mohan <p-mohan@ti.com> + * Md Danish Anwar <danishanwar@ti.com> */ #include <linux/bitops.h> @@ -16,6 +18,7 @@ #include <linux/module.h> #include <linux/of_device.h> #include <linux/of_irq.h> +#include <linux/remoteproc/pruss.h> #include <linux/pruss_driver.h> #include <linux/remoteproc.h> @@ -111,10 +114,13 @@ struct pru_private_data { * @rproc: remoteproc pointer for this PRU core * @data: PRU core specific data * @mem_regions: data for each of the PRU memory regions + * @client_np: client device node + * @lock: mutex to protect client usage * @fw_name: name of firmware image used during loading * @mapped_irq: virtual interrupt numbers of created fw specific mapping * @pru_interrupt_map: pointer to interrupt mapping description (firmware) * @pru_interrupt_map_sz: pru_interrupt_map size + * @rmw_lock: lock for read, modify, write operations on registers * @dbg_single_step: debug state variable to set PRU into single step mode * @dbg_continuous: debug state variable to restore PRU execution mode * @evt_count: number of mapped events @@ -126,10 +132,13 @@ struct pru_rproc { struct rproc *rproc; const struct pru_private_data *data; struct pruss_mem_region mem_regions[PRU_IOMEM_MAX]; + struct device_node *client_np; + struct mutex lock; const char *fw_name; unsigned int *mapped_irq; struct pru_irq_rsc *pru_interrupt_map; size_t pru_interrupt_map_sz; + spinlock_t rmw_lock; u32 dbg_single_step; u32 dbg_continuous; u8 evt_count; @@ -146,6 +155,212 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val) writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg); } +static inline +void pru_control_set_reg(struct pru_rproc *pru, unsigned int reg, + u32 mask, u32 set) +{ + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pru->rmw_lock, flags); + + val = pru_control_read_reg(pru, reg); + val &= ~mask; + val |= (set & mask); + pru_control_write_reg(pru, reg, val); + + spin_unlock_irqrestore(&pru->rmw_lock, flags); +} + +/** + * pru_rproc_set_firmware() - set firmware for a PRU core + * @rproc: the rproc instance of the PRU + * @fw_name: the new firmware name, or NULL if default is desired + * + * Return: 0 on success, or errno in error case. + */ +static int pru_rproc_set_firmware(struct rproc *rproc, const char *fw_name) +{ + struct pru_rproc *pru = rproc->priv; + + if (!fw_name) + fw_name = pru->fw_name; + + return rproc_set_firmware(rproc, fw_name); +} + +static struct rproc *__pru_rproc_get(struct device_node *np, int index) +{ + struct rproc *rproc; + phandle rproc_phandle; + int ret; + + ret = of_property_read_u32_index(np, "ti,prus", index, &rproc_phandle); + if (ret) + return ERR_PTR(ret); + + rproc = rproc_get_by_phandle(rproc_phandle); + if (!rproc) { + ret = -EPROBE_DEFER; + return ERR_PTR(ret); + } + + /* make sure it is PRU rproc */ + if (!is_pru_rproc(rproc->dev.parent)) { + rproc_put(rproc); + return ERR_PTR(-ENODEV); + } + + return rproc; +} + +/** + * pru_rproc_get() - get the PRU rproc instance from a device node + * @np: the user/client device node + * @index: index to use for the ti,prus property + * @pru_id: optional pointer to return the PRU remoteproc processor id + * + * This function looks through a client device node's "ti,prus" property at + * index @index and returns the rproc handle for a valid PRU remote processor if + * found. The function allows only one user to own the PRU rproc resource at a + * time. Caller must call pru_rproc_put() when done with using the rproc, not + * required if the function returns a failure. + * + * When optional @pru_id pointer is passed the PRU remoteproc processor id is + * returned. + * + * Return: rproc handle on success, and an ERR_PTR on failure using one + * of the following error values + * -ENODEV if device is not found + * -EBUSY if PRU is already acquired by anyone + * -EPROBE_DEFER is PRU device is not probed yet + */ +struct rproc *pru_rproc_get(struct device_node *np, int index, + enum pruss_pru_id *pru_id) +{ + struct rproc *rproc; + struct pru_rproc *pru; + struct device *dev; + const char *fw_name; + int ret; + + rproc = __pru_rproc_get(np, index); + if (IS_ERR(rproc)) + return rproc; + + pru = rproc->priv; + dev = &rproc->dev; + + mutex_lock(&pru->lock); + + if (pru->client_np) { + mutex_unlock(&pru->lock); + ret = -EBUSY; + goto err_no_rproc_handle; + } + + pru->client_np = np; + rproc->sysfs_read_only = true; + + mutex_unlock(&pru->lock); + + if (pru_id) + *pru_id = pru->id; + + ret = of_property_read_string_index(np, "firmware-name", index, + &fw_name); + if (!ret) { + ret = pru_rproc_set_firmware(rproc, fw_name); + if (ret) { + dev_err(dev, "failed to set firmware: %d\n", ret); + goto err; + } + } + + return rproc; + +err_no_rproc_handle: + rproc_put(rproc); + return ERR_PTR(ret); + +err: + pru_rproc_put(rproc); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(pru_rproc_get); + +/** + * pru_rproc_put() - release the PRU rproc resource + * @rproc: the rproc resource to release + * + * Releases the PRU rproc resource and makes it available to other + * users. + */ +void pru_rproc_put(struct rproc *rproc) +{ + struct pru_rproc *pru; + + if (IS_ERR_OR_NULL(rproc) || !is_pru_rproc(rproc->dev.parent)) + return; + + pru = rproc->priv; + + pru_rproc_set_firmware(rproc, NULL); + + mutex_lock(&pru->lock); + + if (!pru->client_np) { + mutex_unlock(&pru->lock); + return; + } + + pru->client_np = NULL; + rproc->sysfs_read_only = false; + mutex_unlock(&pru->lock); + + rproc_put(rproc); +} +EXPORT_SYMBOL_GPL(pru_rproc_put); + +/** + * pru_rproc_set_ctable() - set the constant table index for the PRU + * @rproc: the rproc instance of the PRU + * @c: constant table index to set + * @addr: physical address to set it to + * + * Return: 0 on success, or errno in error case. + */ +int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr) +{ + struct pru_rproc *pru = rproc->priv; + unsigned int reg; + u32 mask, set; + u16 idx; + u16 idx_mask; + + if (IS_ERR_OR_NULL(rproc)) + return -EINVAL; + + if (!rproc->dev.parent || !is_pru_rproc(rproc->dev.parent)) + return -ENODEV; + + /* pointer is 16 bit and index is 8-bit so mask out the rest */ + idx_mask = (c >= PRU_C28) ? 0xFFFF : 0xFF; + + /* ctable uses bit 8 and upwards only */ + idx = (addr >> 8) & idx_mask; + + /* configurable ctable (i.e. C24) starts at PRU_CTRL_CTBIR0 */ + reg = PRU_CTRL_CTBIR0 + 4 * (c >> 1); + mask = idx_mask << (16 * (c & 1)); + set = idx << (16 * (c & 1)); + + pru_control_set_reg(pru, reg, mask, set); + + return 0; +} +EXPORT_SYMBOL_GPL(pru_rproc_set_ctable); + static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg) { return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg); @@ -438,7 +653,7 @@ static void *pru_d_da_to_va(struct pru_rproc *pru, u32 da, size_t len) dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0]; dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1]; /* PRU1 has its local RAM addresses reversed */ - if (pru->id == 1) + if (pru->id == PRUSS_PRU1) swap(dram0, dram1); shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2]; @@ -747,14 +962,14 @@ static int pru_rproc_set_id(struct pru_rproc *pru) case RTU0_IRAM_ADDR_MASK: fallthrough; case PRU0_IRAM_ADDR_MASK: - pru->id = 0; + pru->id = PRUSS_PRU0; break; case TX_PRU1_IRAM_ADDR_MASK: fallthrough; case RTU1_IRAM_ADDR_MASK: fallthrough; case PRU1_IRAM_ADDR_MASK: - pru->id = 1; + pru->id = PRUSS_PRU1; break; default: ret = -EINVAL; @@ -816,6 +1031,9 @@ static int pru_rproc_probe(struct platform_device *pdev) pru->pruss = platform_get_drvdata(ppdev); pru->rproc = rproc; pru->fw_name = fw_name; + pru->client_np = NULL; + spin_lock_init(&pru->rmw_lock); + mutex_init(&pru->lock); for (i = 0; i < ARRAY_SIZE(mem_names); i++) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, @@ -904,7 +1122,7 @@ MODULE_DEVICE_TABLE(of, pru_rproc_match); static struct platform_driver pru_rproc_driver = { .driver = { - .name = "pru-rproc", + .name = PRU_RPROC_DRVNAME, .of_match_table = pru_rproc_match, .suppress_bind_attrs = true, }, @@ -916,5 +1134,7 @@ module_platform_driver(pru_rproc_driver); MODULE_AUTHOR("Suman Anna <s-anna@ti.com>"); MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>"); MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>"); +MODULE_AUTHOR("Puranjay Mohan <p-mohan@ti.com>"); +MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>"); MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/remoteproc/qcom_common.c b/drivers/remoteproc/qcom_common.c index 020349f8979d..a0d4238492e9 100644 --- a/drivers/remoteproc/qcom_common.c +++ b/drivers/remoteproc/qcom_common.c @@ -101,7 +101,9 @@ static void qcom_minidump_cleanup(struct rproc *rproc) } } -static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsystem *subsystem) +static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsystem *subsystem, + void (*rproc_dumpfn_t)(struct rproc *rproc, struct rproc_dump_segment *segment, + void *dest, size_t offset, size_t size)) { struct minidump_region __iomem *ptr; struct minidump_region region; @@ -123,15 +125,15 @@ static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsy for (i = 0; i < seg_cnt; i++) { memcpy_fromio(®ion, ptr + i, sizeof(region)); - if (region.valid == MD_REGION_VALID) { - name = kstrdup(region.name, GFP_KERNEL); + if (le32_to_cpu(region.valid) == MD_REGION_VALID) { + name = kstrndup(region.name, MAX_REGION_NAME_LENGTH - 1, GFP_KERNEL); if (!name) { iounmap(ptr); return -ENOMEM; } da = le64_to_cpu(region.address); - size = le32_to_cpu(region.size); - rproc_coredump_add_custom_segment(rproc, da, size, NULL, name); + size = le64_to_cpu(region.size); + rproc_coredump_add_custom_segment(rproc, da, size, rproc_dumpfn_t, name); } } @@ -139,7 +141,10 @@ static int qcom_add_minidump_segments(struct rproc *rproc, struct minidump_subsy return 0; } -void qcom_minidump(struct rproc *rproc, unsigned int minidump_id) +void qcom_minidump(struct rproc *rproc, unsigned int minidump_id, + void (*rproc_dumpfn_t)(struct rproc *rproc, + struct rproc_dump_segment *segment, void *dest, size_t offset, + size_t size)) { int ret; struct minidump_subsystem *subsystem; @@ -169,7 +174,7 @@ void qcom_minidump(struct rproc *rproc, unsigned int minidump_id) return; } - ret = qcom_add_minidump_segments(rproc, subsystem); + ret = qcom_add_minidump_segments(rproc, subsystem, rproc_dumpfn_t); if (ret) { dev_err(&rproc->dev, "Failed with error: %d while adding minidump entries\n", ret); goto clean_minidump; diff --git a/drivers/remoteproc/qcom_common.h b/drivers/remoteproc/qcom_common.h index 2747c7d9ba44..9ef4449052a9 100644 --- a/drivers/remoteproc/qcom_common.h +++ b/drivers/remoteproc/qcom_common.h @@ -34,7 +34,10 @@ struct qcom_rproc_ssr { struct qcom_ssr_subsystem *info; }; -void qcom_minidump(struct rproc *rproc, unsigned int minidump_id); +void qcom_minidump(struct rproc *rproc, unsigned int minidump_id, + void (*rproc_dumpfn_t)(struct rproc *rproc, + struct rproc_dump_segment *segment, void *dest, size_t offset, + size_t size)); void qcom_add_glink_subdev(struct rproc *rproc, struct qcom_rproc_glink *glink, const char *ssr_name); diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index 497acfb33f8f..192c7aa0e39e 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -205,8 +205,8 @@ int qcom_q6v5_request_stop(struct qcom_q6v5 *q6v5, struct qcom_sysmon *sysmon) q6v5->running = false; - /* Don't perform SMP2P dance if sysmon already shut down the remote */ - if (qcom_sysmon_shutdown_acked(sysmon)) + /* Don't perform SMP2P dance if remote isn't running */ + if (q6v5->rproc->state != RPROC_RUNNING || qcom_sysmon_shutdown_acked(sysmon)) return 0; qcom_smem_state_update_bits(q6v5->state, diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index 4c9a1b99cd51..08d8dad22ca7 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -9,6 +9,7 @@ #include <linux/firmware.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/iommu.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> @@ -48,12 +49,18 @@ #define LPASS_PWR_ON_REG 0x10 #define LPASS_HALTREQ_REG 0x0 +#define SID_MASK_DEFAULT 0xF + #define QDSP6SS_XO_CBCR 0x38 #define QDSP6SS_CORE_CBCR 0x20 #define QDSP6SS_SLEEP_CBCR 0x3c #define QCOM_Q6V5_RPROC_PROXY_PD_MAX 3 +#define LPASS_BOOT_CORE_START BIT(0) +#define LPASS_BOOT_CMD_START BIT(0) +#define LPASS_EFUSE_Q6SS_EVB_SEL 0x0 + struct adsp_pil_data { int crash_reason_smem; const char *firmware_name; @@ -62,6 +69,7 @@ struct adsp_pil_data { const char *sysmon_name; int ssctl_id; bool is_wpss; + bool has_iommu; bool auto_boot; const char **clk_ids; @@ -82,6 +90,7 @@ struct qcom_adsp { struct clk_bulk_data *clks; void __iomem *qdsp6ss_base; + void __iomem *lpass_efuse; struct reset_control *pdc_sync_reset; struct reset_control *restart; @@ -99,6 +108,7 @@ struct qcom_adsp { phys_addr_t mem_reloc; void *mem_region; size_t mem_size; + bool has_iommu; struct device *proxy_pds[QCOM_Q6V5_RPROC_PROXY_PD_MAX]; size_t proxy_pd_count; @@ -325,6 +335,48 @@ static int adsp_load(struct rproc *rproc, const struct firmware *fw) return 0; } +static void adsp_unmap_carveout(struct rproc *rproc) +{ + struct qcom_adsp *adsp = rproc->priv; + + if (adsp->has_iommu) + iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size); +} + +static int adsp_map_carveout(struct rproc *rproc) +{ + struct qcom_adsp *adsp = rproc->priv; + struct of_phandle_args args; + long long sid; + unsigned long iova; + int ret; + + if (!adsp->has_iommu) + return 0; + + if (!rproc->domain) + return -EINVAL; + + ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args); + if (ret < 0) + return ret; + + sid = args.args[0] & SID_MASK_DEFAULT; + + /* Add SID configuration for ADSP Firmware to SMMU */ + iova = adsp->mem_phys | (sid << 32); + + ret = iommu_map(rproc->domain, iova, adsp->mem_phys, + adsp->mem_size, IOMMU_READ | IOMMU_WRITE, + GFP_KERNEL); + if (ret) { + dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n"); + return ret; + } + + return 0; +} + static int adsp_start(struct rproc *rproc) { struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; @@ -335,9 +387,15 @@ static int adsp_start(struct rproc *rproc) if (ret) return ret; + ret = adsp_map_carveout(rproc); + if (ret) { + dev_err(adsp->dev, "ADSP smmu mapping failed\n"); + goto disable_irqs; + } + ret = clk_prepare_enable(adsp->xo); if (ret) - goto disable_irqs; + goto adsp_smmu_unmap; ret = qcom_rproc_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); @@ -362,11 +420,14 @@ static int adsp_start(struct rproc *rproc) /* Program boot address */ writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG); + if (adsp->lpass_efuse) + writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse); + /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */ - writel(0x1, adsp->qdsp6ss_base + CORE_START_REG); + writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG); /* Trigger boot FSM to start QDSP6 */ - writel(0x1, adsp->qdsp6ss_base + BOOT_CMD_REG); + writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG); /* Wait for core to come out of reset */ ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG, @@ -390,6 +451,8 @@ disable_power_domain: qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); disable_xo_clk: clk_disable_unprepare(adsp->xo); +adsp_smmu_unmap: + adsp_unmap_carveout(rproc); disable_irqs: qcom_q6v5_unprepare(&adsp->q6v5); @@ -418,6 +481,8 @@ static int adsp_stop(struct rproc *rproc) if (ret) dev_err(adsp->dev, "failed to shutdown: %d\n", ret); + adsp_unmap_carveout(rproc); + handover = qcom_q6v5_unprepare(&adsp->q6v5); if (handover) qcom_adsp_pil_handover(&adsp->q6v5); @@ -437,6 +502,27 @@ static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iom return adsp->mem_region + offset; } +static int adsp_parse_firmware(struct rproc *rproc, const struct firmware *fw) +{ + struct qcom_adsp *adsp = rproc->priv; + int ret; + + ret = qcom_register_dump_segments(rproc, fw); + if (ret) { + dev_err(&rproc->dev, "Error in registering dump segments\n"); + return ret; + } + + if (adsp->has_iommu) { + ret = rproc_elf_load_rsc_table(rproc, fw); + if (ret) { + dev_err(&rproc->dev, "Error in loading resource table\n"); + return ret; + } + } + return 0; +} + static unsigned long adsp_panic(struct rproc *rproc) { struct qcom_adsp *adsp = rproc->priv; @@ -448,7 +534,7 @@ static const struct rproc_ops adsp_ops = { .start = adsp_start, .stop = adsp_stop, .da_to_va = adsp_da_to_va, - .parse_fw = qcom_register_dump_segments, + .parse_fw = adsp_parse_firmware, .load = adsp_load, .panic = adsp_panic, }; @@ -507,6 +593,7 @@ static int adsp_init_reset(struct qcom_adsp *adsp) static int adsp_init_mmio(struct qcom_adsp *adsp, struct platform_device *pdev) { + struct resource *efuse_region; struct device_node *syscon; int ret; @@ -516,6 +603,17 @@ static int adsp_init_mmio(struct qcom_adsp *adsp, return PTR_ERR(adsp->qdsp6ss_base); } + efuse_region = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!efuse_region) { + adsp->lpass_efuse = NULL; + dev_dbg(adsp->dev, "failed to get efuse memory region\n"); + } else { + adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region); + if (IS_ERR(adsp->lpass_efuse)) { + dev_err(adsp->dev, "failed to map efuse registers\n"); + return PTR_ERR(adsp->lpass_efuse); + } + } syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0); if (!syscon) { dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); @@ -595,12 +693,15 @@ static int adsp_probe(struct platform_device *pdev) } rproc->auto_boot = desc->auto_boot; + rproc->has_iommu = desc->has_iommu; rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); adsp = (struct qcom_adsp *)rproc->priv; adsp->dev = &pdev->dev; adsp->rproc = rproc; adsp->info_name = desc->sysmon_name; + adsp->has_iommu = desc->has_iommu; + platform_set_drvdata(pdev, adsp); if (desc->is_wpss) @@ -696,6 +797,21 @@ static const struct adsp_pil_data adsp_resource_init = { }, }; +static const struct adsp_pil_data adsp_sc7280_resource_init = { + .crash_reason_smem = 423, + .firmware_name = "adsp.pbn", + .load_state = "adsp", + .ssr_name = "lpass", + .sysmon_name = "adsp", + .ssctl_id = 0x14, + .has_iommu = true, + .auto_boot = true, + .clk_ids = (const char*[]) { + "gcc_cfg_noc_lpass", NULL + }, + .num_clks = 1, +}; + static const struct adsp_pil_data cdsp_resource_init = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", @@ -734,6 +850,7 @@ static const struct adsp_pil_data wpss_resource_init = { static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init }, + { .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init }, { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init }, { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init }, { }, diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index fddb63cffee0..292e22f58df3 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -10,7 +10,6 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/devcoredump.h> -#include <linux/dma-map-ops.h> #include <linux/dma-mapping.h> #include <linux/interrupt.h> #include <linux/kernel.h> @@ -18,6 +17,7 @@ #include <linux/module.h> #include <linux/of_address.h> #include <linux/of_device.h> +#include <linux/of_reserved_mem.h> #include <linux/platform_device.h> #include <linux/pm_domain.h> #include <linux/pm_runtime.h> @@ -40,6 +40,8 @@ #define MBA_LOG_SIZE SZ_4K +#define MPSS_PAS_ID 5 + /* RMB Status Register Values */ #define RMB_PBL_SUCCESS 0x1 @@ -111,6 +113,9 @@ #define QDSS_BHS_ON BIT(21) #define QDSS_LDO_BYP BIT(22) +/* QDSP6v55 parameters */ +#define QDSP6V55_MEM_BITS GENMASK(16, 8) + /* QDSP6v56 parameters */ #define QDSP6v56_LDO_BYP BIT(25) #define QDSP6v56_BHS_ON BIT(24) @@ -211,6 +216,9 @@ struct q6v5 { size_t mba_size; size_t dp_size; + phys_addr_t mdata_phys; + size_t mdata_size; + phys_addr_t mpss_phys; phys_addr_t mpss_reloc; size_t mpss_size; @@ -234,7 +242,9 @@ struct q6v5 { }; enum { + MSS_MSM8909, MSS_MSM8916, + MSS_MSM8953, MSS_MSM8974, MSS_MSM8996, MSS_MSM8998, @@ -687,13 +697,16 @@ static int q6v5proc_reset(struct q6v5 *qproc) return ret; } goto pbl_wait; - } else if (qproc->version == MSS_MSM8996 || + } else if (qproc->version == MSS_MSM8909 || + qproc->version == MSS_MSM8953 || + qproc->version == MSS_MSM8996 || qproc->version == MSS_MSM8998) { - int mem_pwr_ctl; - /* Override the ACC value if required */ - writel(QDSP6SS_ACC_OVERRIDE_VAL, - qproc->reg_base + QDSP6SS_STRAP_ACC); + if (qproc->version != MSS_MSM8909 && + qproc->version != MSS_MSM8953) + /* Override the ACC value if required */ + writel(QDSP6SS_ACC_OVERRIDE_VAL, + qproc->reg_base + QDSP6SS_STRAP_ACC); /* Assert resets, stop core */ val = readl(qproc->reg_base + QDSP6SS_RESET_REG); @@ -725,36 +738,54 @@ static int q6v5proc_reset(struct q6v5 *qproc) val |= QDSP6v56_LDO_BYP; writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - /* Deassert QDSP6 compiler memory clamp */ - val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); - val &= ~QDSP6v56_CLAMP_QMC_MEM; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - - /* Deassert memory peripheral sleep and L2 memory standby */ - val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; - writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); - - /* Turn on L1, L2, ETB and JU memories 1 at a time */ - if (qproc->version == MSS_MSM8996) { - mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL; - i = 19; + if (qproc->version != MSS_MSM8909) { + int mem_pwr_ctl; + + /* Deassert QDSP6 compiler memory clamp */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val &= ~QDSP6v56_CLAMP_QMC_MEM; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Deassert memory peripheral sleep and L2 memory standby */ + val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Turn on L1, L2, ETB and JU memories 1 at a time */ + if (qproc->version == MSS_MSM8953 || + qproc->version == MSS_MSM8996) { + mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL; + i = 19; + } else { + /* MSS_MSM8998 */ + mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL; + i = 28; + } + val = readl(qproc->reg_base + mem_pwr_ctl); + for (; i >= 0; i--) { + val |= BIT(i); + writel(val, qproc->reg_base + mem_pwr_ctl); + /* + * Read back value to ensure the write is done then + * wait for 1us for both memory peripheral and data + * array to turn on. + */ + val |= readl(qproc->reg_base + mem_pwr_ctl); + udelay(1); + } } else { - /* MSS_MSM8998 */ - mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL; - i = 28; - } - val = readl(qproc->reg_base + mem_pwr_ctl); - for (; i >= 0; i--) { - val |= BIT(i); - writel(val, qproc->reg_base + mem_pwr_ctl); - /* - * Read back value to ensure the write is done then - * wait for 1us for both memory peripheral and data - * array to turn on. - */ - val |= readl(qproc->reg_base + mem_pwr_ctl); - udelay(1); + /* Turn on memories */ + val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); + val |= Q6SS_SLP_RET_N | Q6SS_L2DATA_STBY_N | + Q6SS_ETB_SLP_NRET_N | QDSP6V55_MEM_BITS; + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + + /* Turn on L2 banks 1 at a time */ + for (i = 0; i <= 7; i++) { + val |= BIT(i); + writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); + } } + /* Remove word line clamp */ val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); val &= ~QDSP6v56_CLAMP_WL; @@ -933,52 +964,47 @@ static void q6v5proc_halt_axi_port(struct q6v5 *qproc, static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw, const char *fw_name) { - unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS | DMA_ATTR_NO_KERNEL_MAPPING; - unsigned long flags = VM_DMA_COHERENT | VM_FLUSH_RESET_PERMS; - struct page **pages; - struct page *page; + unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; dma_addr_t phys; void *metadata; int mdata_perm; int xferop_ret; size_t size; - void *vaddr; - int count; + void *ptr; int ret; - int i; metadata = qcom_mdt_read_metadata(fw, &size, fw_name, qproc->dev); if (IS_ERR(metadata)) return PTR_ERR(metadata); - page = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs); - if (!page) { - kfree(metadata); - dev_err(qproc->dev, "failed to allocate mdt buffer\n"); - return -ENOMEM; - } - - count = PAGE_ALIGN(size) >> PAGE_SHIFT; - pages = kmalloc_array(count, sizeof(struct page *), GFP_KERNEL); - if (!pages) { - ret = -ENOMEM; - goto free_dma_attrs; - } - - for (i = 0; i < count; i++) - pages[i] = nth_page(page, i); + if (qproc->mdata_phys) { + if (size > qproc->mdata_size) { + ret = -EINVAL; + dev_err(qproc->dev, "metadata size outside memory range\n"); + goto free_metadata; + } - vaddr = vmap(pages, count, flags, pgprot_dmacoherent(PAGE_KERNEL)); - kfree(pages); - if (!vaddr) { - dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", &phys, size); - ret = -EBUSY; - goto free_dma_attrs; + phys = qproc->mdata_phys; + ptr = memremap(qproc->mdata_phys, size, MEMREMAP_WC); + if (!ptr) { + ret = -EBUSY; + dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", + &qproc->mdata_phys, size); + goto free_metadata; + } + } else { + ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs); + if (!ptr) { + ret = -ENOMEM; + dev_err(qproc->dev, "failed to allocate mdt buffer\n"); + goto free_metadata; + } } - memcpy(vaddr, metadata, size); + memcpy(ptr, metadata, size); - vunmap(vaddr); + if (qproc->mdata_phys) + memunmap(ptr); /* Hypervisor mapping to access metadata by modem */ mdata_perm = BIT(QCOM_SCM_VMID_HLOS); @@ -1008,7 +1034,9 @@ static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw, "mdt buffer not reclaimed system may become unstable\n"); free_dma_attrs: - dma_free_attrs(qproc->dev, size, page, phys, dma_attrs); + if (!qproc->mdata_phys) + dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs); +free_metadata: kfree(metadata); return ret < 0 ? ret : 0; @@ -1343,6 +1371,15 @@ static int q6v5_mpss_load(struct q6v5 *qproc) max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); } + if (qproc->version == MSS_MSM8953) { + ret = qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_size); + if (ret) { + dev_err(qproc->dev, + "setting up mpss memory failed: %d\n", ret); + goto release_firmware; + } + } + /* * In case of a modem subsystem restart on secure devices, the modem * memory can be reclaimed only after MBA is loaded. @@ -1836,6 +1873,7 @@ static int q6v5_init_reset(struct q6v5 *qproc) static int q6v5_alloc_memory_region(struct q6v5 *qproc) { struct device_node *child; + struct reserved_mem *rmem; struct device_node *node; struct resource r; int ret; @@ -1882,6 +1920,26 @@ static int q6v5_alloc_memory_region(struct q6v5 *qproc) qproc->mpss_phys = qproc->mpss_reloc = r.start; qproc->mpss_size = resource_size(&r); + if (!child) { + node = of_parse_phandle(qproc->dev->of_node, "memory-region", 2); + } else { + child = of_get_child_by_name(qproc->dev->of_node, "metadata"); + node = of_parse_phandle(child, "memory-region", 0); + of_node_put(child); + } + + if (!node) + return 0; + + rmem = of_reserved_mem_lookup(node); + if (!rmem) { + dev_err(qproc->dev, "unable to resolve metadata region\n"); + return -EINVAL; + } + + qproc->mdata_phys = rmem->base; + qproc->mdata_size = rmem->size; + return 0; } @@ -2240,6 +2298,40 @@ static const struct rproc_hexagon_res msm8996_mss = { .version = MSS_MSM8996, }; +static const struct rproc_hexagon_res msm8909_mss = { + .hexagon_mba_image = "mba.mbn", + .proxy_supply = (struct qcom_mss_reg_res[]) { + { + .supply = "pll", + .uA = 100000, + }, + {} + }, + .proxy_clk_names = (char*[]){ + "xo", + NULL + }, + .active_clk_names = (char*[]){ + "iface", + "bus", + "mem", + NULL + }, + .proxy_pd_names = (char*[]){ + "mx", + "cx", + NULL + }, + .need_mem_protection = false, + .has_alt_reset = false, + .has_mba_logs = false, + .has_spare_reg = false, + .has_qaccept_regs = false, + .has_ext_cntl_regs = false, + .has_vq6 = false, + .version = MSS_MSM8909, +}; + static const struct rproc_hexagon_res msm8916_mss = { .hexagon_mba_image = "mba.mbn", .proxy_supply = (struct qcom_mss_reg_res[]) { @@ -2285,6 +2377,41 @@ static const struct rproc_hexagon_res msm8916_mss = { .version = MSS_MSM8916, }; +static const struct rproc_hexagon_res msm8953_mss = { + .hexagon_mba_image = "mba.mbn", + .proxy_supply = (struct qcom_mss_reg_res[]) { + { + .supply = "pll", + .uA = 100000, + }, + {} + }, + .proxy_clk_names = (char*[]){ + "xo", + NULL + }, + .active_clk_names = (char*[]){ + "iface", + "bus", + "mem", + NULL + }, + .proxy_pd_names = (char*[]) { + "cx", + "mx", + "mss", + NULL + }, + .need_mem_protection = false, + .has_alt_reset = false, + .has_mba_logs = false, + .has_spare_reg = false, + .has_qaccept_regs = false, + .has_ext_cntl_regs = false, + .has_vq6 = false, + .version = MSS_MSM8953, +}; + static const struct rproc_hexagon_res msm8974_mss = { .hexagon_mba_image = "mba.b00", .proxy_supply = (struct qcom_mss_reg_res[]) { @@ -2340,7 +2467,9 @@ static const struct rproc_hexagon_res msm8974_mss = { static const struct of_device_id q6v5_of_match[] = { { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, + { .compatible = "qcom,msm8909-mss-pil", .data = &msm8909_mss}, { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, + { .compatible = "qcom,msm8953-mss-pil", .data = &msm8953_mss}, { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss}, diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index dc6f07ca8341..6cc4e13c5d36 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -35,9 +35,10 @@ struct adsp_data { int crash_reason_smem; const char *firmware_name; + const char *dtb_firmware_name; int pas_id; + int dtb_pas_id; unsigned int minidump_id; - bool has_aggre2_clk; bool auto_boot; bool decrypt_shutdown; @@ -47,6 +48,8 @@ struct adsp_data { const char *ssr_name; const char *sysmon_name; int ssctl_id; + + int region_assign_idx; }; struct qcom_adsp { @@ -65,20 +68,33 @@ struct qcom_adsp { int proxy_pd_count; + const char *dtb_firmware_name; int pas_id; + int dtb_pas_id; unsigned int minidump_id; int crash_reason_smem; - bool has_aggre2_clk; bool decrypt_shutdown; const char *info_name; + const struct firmware *firmware; + const struct firmware *dtb_firmware; + struct completion start_done; struct completion stop_done; phys_addr_t mem_phys; + phys_addr_t dtb_mem_phys; phys_addr_t mem_reloc; + phys_addr_t dtb_mem_reloc; + phys_addr_t region_assign_phys; void *mem_region; + void *dtb_mem_region; size_t mem_size; + size_t dtb_mem_size; + size_t region_assign_size; + + int region_assign_idx; + int region_assign_perms; struct qcom_rproc_glink glink_subdev; struct qcom_rproc_subdev smd_subdev; @@ -86,8 +102,27 @@ struct qcom_adsp { struct qcom_sysmon *sysmon; struct qcom_scm_pas_metadata pas_metadata; + struct qcom_scm_pas_metadata dtb_pas_metadata; }; +void adsp_segment_dump(struct rproc *rproc, struct rproc_dump_segment *segment, + void *dest, size_t offset, size_t size) +{ + struct qcom_adsp *adsp = rproc->priv; + int total_offset; + + total_offset = segment->da + segment->offset + offset - adsp->mem_phys; + if (total_offset < 0 || total_offset + size > adsp->mem_size) { + dev_err(adsp->dev, + "invalid copy request for segment %pad with offset %zu and size %zu)\n", + &segment->da, offset, size); + memset(dest, 0xff, size); + return; + } + + memcpy_fromio(dest, adsp->mem_region + total_offset, size); +} + static void adsp_minidump(struct rproc *rproc) { struct qcom_adsp *adsp = rproc->priv; @@ -95,7 +130,7 @@ static void adsp_minidump(struct rproc *rproc) if (rproc->dump_conf == RPROC_COREDUMP_DISABLED) return; - qcom_minidump(rproc, adsp->minidump_id); + qcom_minidump(rproc, adsp->minidump_id, adsp_segment_dump); } static int adsp_pds_enable(struct qcom_adsp *adsp, struct device **pds, @@ -160,6 +195,8 @@ static int adsp_unprepare(struct rproc *rproc) * here. */ qcom_scm_pas_metadata_release(&adsp->pas_metadata); + if (adsp->dtb_pas_id) + qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata); return 0; } @@ -169,20 +206,40 @@ static int adsp_load(struct rproc *rproc, const struct firmware *fw) struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; int ret; - ret = qcom_mdt_pas_init(adsp->dev, fw, rproc->firmware, adsp->pas_id, - adsp->mem_phys, &adsp->pas_metadata); - if (ret) - return ret; + /* Store firmware handle to be used in adsp_start() */ + adsp->firmware = fw; - ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, adsp->pas_id, - adsp->mem_region, adsp->mem_phys, adsp->mem_size, - &adsp->mem_reloc); - if (ret) - return ret; + if (adsp->dtb_pas_id) { + ret = request_firmware(&adsp->dtb_firmware, adsp->dtb_firmware_name, adsp->dev); + if (ret) { + dev_err(adsp->dev, "request_firmware failed for %s: %d\n", + adsp->dtb_firmware_name, ret); + return ret; + } - qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); + ret = qcom_mdt_pas_init(adsp->dev, adsp->dtb_firmware, adsp->dtb_firmware_name, + adsp->dtb_pas_id, adsp->dtb_mem_phys, + &adsp->dtb_pas_metadata); + if (ret) + goto release_dtb_firmware; + + ret = qcom_mdt_load_no_init(adsp->dev, adsp->dtb_firmware, adsp->dtb_firmware_name, + adsp->dtb_pas_id, adsp->dtb_mem_region, + adsp->dtb_mem_phys, adsp->dtb_mem_size, + &adsp->dtb_mem_reloc); + if (ret) + goto release_dtb_metadata; + } return 0; + +release_dtb_metadata: + qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata); + +release_dtb_firmware: + release_firmware(adsp->dtb_firmware); + + return ret; } static int adsp_start(struct rproc *rproc) @@ -218,24 +275,55 @@ static int adsp_start(struct rproc *rproc) goto disable_cx_supply; } + if (adsp->dtb_pas_id) { + ret = qcom_scm_pas_auth_and_reset(adsp->dtb_pas_id); + if (ret) { + dev_err(adsp->dev, + "failed to authenticate dtb image and release reset\n"); + goto disable_px_supply; + } + } + + ret = qcom_mdt_pas_init(adsp->dev, adsp->firmware, rproc->firmware, adsp->pas_id, + adsp->mem_phys, &adsp->pas_metadata); + if (ret) + goto disable_px_supply; + + ret = qcom_mdt_load_no_init(adsp->dev, adsp->firmware, rproc->firmware, adsp->pas_id, + adsp->mem_region, adsp->mem_phys, adsp->mem_size, + &adsp->mem_reloc); + if (ret) + goto release_pas_metadata; + + qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size); + ret = qcom_scm_pas_auth_and_reset(adsp->pas_id); if (ret) { dev_err(adsp->dev, "failed to authenticate image and release reset\n"); - goto disable_px_supply; + goto release_pas_metadata; } ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5000)); if (ret == -ETIMEDOUT) { dev_err(adsp->dev, "start timed out\n"); qcom_scm_pas_shutdown(adsp->pas_id); - goto disable_px_supply; + goto release_pas_metadata; } qcom_scm_pas_metadata_release(&adsp->pas_metadata); + if (adsp->dtb_pas_id) + qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata); + + /* Remove pointer to the loaded firmware, only valid in adsp_load() & adsp_start() */ + adsp->firmware = NULL; return 0; +release_pas_metadata: + qcom_scm_pas_metadata_release(&adsp->pas_metadata); + if (adsp->dtb_pas_id) + qcom_scm_pas_metadata_release(&adsp->dtb_pas_metadata); disable_px_supply: if (adsp->px_supply) regulator_disable(adsp->px_supply); @@ -251,6 +339,9 @@ disable_proxy_pds: disable_irqs: qcom_q6v5_unprepare(&adsp->q6v5); + /* Remove pointer to the loaded firmware, only valid in adsp_load() & adsp_start() */ + adsp->firmware = NULL; + return ret; } @@ -284,6 +375,12 @@ static int adsp_stop(struct rproc *rproc) if (ret) dev_err(adsp->dev, "failed to shutdown: %d\n", ret); + if (adsp->dtb_pas_id) { + ret = qcom_scm_pas_shutdown(adsp->dtb_pas_id); + if (ret) + dev_err(adsp->dev, "failed to shutdown dtb: %d\n", ret); + } + handover = qcom_q6v5_unprepare(&adsp->q6v5); if (handover) qcom_pas_handover(&adsp->q6v5); @@ -345,15 +442,13 @@ static int adsp_init_clock(struct qcom_adsp *adsp) return ret; } - if (adsp->has_aggre2_clk) { - adsp->aggre2_clk = devm_clk_get(adsp->dev, "aggre2"); - if (IS_ERR(adsp->aggre2_clk)) { - ret = PTR_ERR(adsp->aggre2_clk); - if (ret != -EPROBE_DEFER) - dev_err(adsp->dev, - "failed to get aggre2 clock"); - return ret; - } + adsp->aggre2_clk = devm_clk_get_optional(adsp->dev, "aggre2"); + if (IS_ERR(adsp->aggre2_clk)) { + ret = PTR_ERR(adsp->aggre2_clk); + if (ret != -EPROBE_DEFER) + dev_err(adsp->dev, + "failed to get aggre2 clock"); + return ret; } return 0; @@ -462,15 +557,95 @@ static int adsp_alloc_memory_region(struct qcom_adsp *adsp) return -EBUSY; } + if (!adsp->dtb_pas_id) + return 0; + + node = of_parse_phandle(adsp->dev->of_node, "memory-region", 1); + if (!node) { + dev_err(adsp->dev, "no dtb memory-region specified\n"); + return -EINVAL; + } + + ret = of_address_to_resource(node, 0, &r); + if (ret) + return ret; + + adsp->dtb_mem_phys = adsp->dtb_mem_reloc = r.start; + adsp->dtb_mem_size = resource_size(&r); + adsp->dtb_mem_region = devm_ioremap_wc(adsp->dev, adsp->dtb_mem_phys, adsp->dtb_mem_size); + if (!adsp->dtb_mem_region) { + dev_err(adsp->dev, "unable to map dtb memory region: %pa+%zx\n", + &r.start, adsp->dtb_mem_size); + return -EBUSY; + } + return 0; } +static int adsp_assign_memory_region(struct qcom_adsp *adsp) +{ + struct qcom_scm_vmperm perm; + struct device_node *node; + struct resource r; + int ret; + + if (!adsp->region_assign_idx) + return 0; + + node = of_parse_phandle(adsp->dev->of_node, "memory-region", adsp->region_assign_idx); + if (!node) { + dev_err(adsp->dev, "missing shareable memory-region\n"); + return -EINVAL; + } + + ret = of_address_to_resource(node, 0, &r); + if (ret) + return ret; + + perm.vmid = QCOM_SCM_VMID_MSS_MSA; + perm.perm = QCOM_SCM_PERM_RW; + + adsp->region_assign_phys = r.start; + adsp->region_assign_size = resource_size(&r); + adsp->region_assign_perms = BIT(QCOM_SCM_VMID_HLOS); + + ret = qcom_scm_assign_mem(adsp->region_assign_phys, + adsp->region_assign_size, + &adsp->region_assign_perms, + &perm, 1); + if (ret < 0) { + dev_err(adsp->dev, "assign memory failed\n"); + return ret; + } + + return 0; +} + +static void adsp_unassign_memory_region(struct qcom_adsp *adsp) +{ + struct qcom_scm_vmperm perm; + int ret; + + if (!adsp->region_assign_idx) + return; + + perm.vmid = QCOM_SCM_VMID_HLOS; + perm.perm = QCOM_SCM_PERM_RW; + + ret = qcom_scm_assign_mem(adsp->region_assign_phys, + adsp->region_assign_size, + &adsp->region_assign_perms, + &perm, 1); + if (ret < 0) + dev_err(adsp->dev, "unassign memory failed\n"); +} + static int adsp_probe(struct platform_device *pdev) { const struct adsp_data *desc; struct qcom_adsp *adsp; struct rproc *rproc; - const char *fw_name; + const char *fw_name, *dtb_fw_name = NULL; const struct rproc_ops *ops = &adsp_ops; int ret; @@ -487,6 +662,14 @@ static int adsp_probe(struct platform_device *pdev) if (ret < 0 && ret != -EINVAL) return ret; + if (desc->dtb_firmware_name) { + dtb_fw_name = desc->dtb_firmware_name; + ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name", 1, + &dtb_fw_name); + if (ret < 0 && ret != -EINVAL) + return ret; + } + if (desc->minidump_id) ops = &adsp_minidump_ops; @@ -505,9 +688,13 @@ static int adsp_probe(struct platform_device *pdev) adsp->rproc = rproc; adsp->minidump_id = desc->minidump_id; adsp->pas_id = desc->pas_id; - adsp->has_aggre2_clk = desc->has_aggre2_clk; adsp->info_name = desc->sysmon_name; adsp->decrypt_shutdown = desc->decrypt_shutdown; + adsp->region_assign_idx = desc->region_assign_idx; + if (dtb_fw_name) { + adsp->dtb_firmware_name = dtb_fw_name; + adsp->dtb_pas_id = desc->dtb_pas_id; + } platform_set_drvdata(pdev, adsp); ret = device_init_wakeup(adsp->dev, true); @@ -518,6 +705,10 @@ static int adsp_probe(struct platform_device *pdev) if (ret) goto free_rproc; + ret = adsp_assign_memory_region(adsp); + if (ret) + goto free_rproc; + ret = adsp_init_clock(adsp); if (ret) goto free_rproc; @@ -539,7 +730,6 @@ static int adsp_probe(struct platform_device *pdev) qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name); qcom_add_smd_subdev(rproc, &adsp->smd_subdev); - qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name); adsp->sysmon = qcom_add_sysmon_subdev(rproc, desc->sysmon_name, desc->ssctl_id); @@ -548,6 +738,7 @@ static int adsp_probe(struct platform_device *pdev) goto detach_proxy_pds; } + qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name); ret = rproc_add(rproc); if (ret) goto detach_proxy_pds; @@ -570,6 +761,7 @@ static int adsp_remove(struct platform_device *pdev) rproc_del(adsp->rproc); qcom_q6v5_deinit(&adsp->q6v5); + adsp_unassign_memory_region(adsp); qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev); qcom_remove_sysmon_subdev(adsp->sysmon); qcom_remove_smd_subdev(adsp->rproc, &adsp->smd_subdev); @@ -585,7 +777,6 @@ static const struct adsp_data adsp_resource_init = { .crash_reason_smem = 423, .firmware_name = "adsp.mdt", .pas_id = 1, - .has_aggre2_clk = false, .auto_boot = true, .ssr_name = "lpass", .sysmon_name = "adsp", @@ -596,7 +787,6 @@ static const struct adsp_data sdm845_adsp_resource_init = { .crash_reason_smem = 423, .firmware_name = "adsp.mdt", .pas_id = 1, - .has_aggre2_clk = false, .auto_boot = true, .load_state = "adsp", .ssr_name = "lpass", @@ -608,7 +798,6 @@ static const struct adsp_data sm6350_adsp_resource = { .crash_reason_smem = 423, .firmware_name = "adsp.mdt", .pas_id = 1, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "lcx", @@ -625,7 +814,6 @@ static const struct adsp_data sm8150_adsp_resource = { .crash_reason_smem = 423, .firmware_name = "adsp.mdt", .pas_id = 1, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "cx", @@ -641,7 +829,6 @@ static const struct adsp_data sm8250_adsp_resource = { .crash_reason_smem = 423, .firmware_name = "adsp.mdt", .pas_id = 1, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "lcx", @@ -658,7 +845,6 @@ static const struct adsp_data sm8350_adsp_resource = { .crash_reason_smem = 423, .firmware_name = "adsp.mdt", .pas_id = 1, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "lcx", @@ -675,7 +861,6 @@ static const struct adsp_data msm8996_adsp_resource = { .crash_reason_smem = 423, .firmware_name = "adsp.mdt", .pas_id = 1, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "cx", @@ -690,7 +875,6 @@ static const struct adsp_data cdsp_resource_init = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", .pas_id = 18, - .has_aggre2_clk = false, .auto_boot = true, .ssr_name = "cdsp", .sysmon_name = "cdsp", @@ -701,7 +885,6 @@ static const struct adsp_data sdm845_cdsp_resource_init = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", .pas_id = 18, - .has_aggre2_clk = false, .auto_boot = true, .load_state = "cdsp", .ssr_name = "cdsp", @@ -713,7 +896,6 @@ static const struct adsp_data sm6350_cdsp_resource = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", .pas_id = 18, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "cx", @@ -730,7 +912,6 @@ static const struct adsp_data sm8150_cdsp_resource = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", .pas_id = 18, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "cx", @@ -746,7 +927,6 @@ static const struct adsp_data sm8250_cdsp_resource = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", .pas_id = 18, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "cx", @@ -762,7 +942,6 @@ static const struct adsp_data sc8280xp_nsp0_resource = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", .pas_id = 18, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "nsp", @@ -777,7 +956,6 @@ static const struct adsp_data sc8280xp_nsp1_resource = { .crash_reason_smem = 633, .firmware_name = "cdsp.mdt", .pas_id = 30, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "nsp", @@ -792,7 +970,6 @@ static const struct adsp_data sm8350_cdsp_resource = { .crash_reason_smem = 601, .firmware_name = "cdsp.mdt", .pas_id = 18, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "cx", @@ -810,7 +987,6 @@ static const struct adsp_data mpss_resource_init = { .firmware_name = "modem.mdt", .pas_id = 4, .minidump_id = 3, - .has_aggre2_clk = false, .auto_boot = false, .proxy_pd_names = (char*[]){ "cx", @@ -827,7 +1003,6 @@ static const struct adsp_data sc8180x_mpss_resource = { .crash_reason_smem = 421, .firmware_name = "modem.mdt", .pas_id = 4, - .has_aggre2_clk = false, .auto_boot = false, .proxy_pd_names = (char*[]){ "cx", @@ -843,7 +1018,6 @@ static const struct adsp_data slpi_resource_init = { .crash_reason_smem = 424, .firmware_name = "slpi.mdt", .pas_id = 12, - .has_aggre2_clk = true, .auto_boot = true, .proxy_pd_names = (char*[]){ "ssc_cx", @@ -858,7 +1032,6 @@ static const struct adsp_data sm8150_slpi_resource = { .crash_reason_smem = 424, .firmware_name = "slpi.mdt", .pas_id = 12, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "lcx", @@ -875,7 +1048,6 @@ static const struct adsp_data sm8250_slpi_resource = { .crash_reason_smem = 424, .firmware_name = "slpi.mdt", .pas_id = 12, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "lcx", @@ -892,7 +1064,6 @@ static const struct adsp_data sm8350_slpi_resource = { .crash_reason_smem = 424, .firmware_name = "slpi.mdt", .pas_id = 12, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "lcx", @@ -919,7 +1090,6 @@ static const struct adsp_data sdx55_mpss_resource = { .crash_reason_smem = 421, .firmware_name = "modem.mdt", .pas_id = 4, - .has_aggre2_clk = false, .auto_boot = true, .proxy_pd_names = (char*[]){ "cx", @@ -936,7 +1106,6 @@ static const struct adsp_data sm8450_mpss_resource = { .firmware_name = "modem.mdt", .pas_id = 4, .minidump_id = 3, - .has_aggre2_clk = false, .auto_boot = false, .decrypt_shutdown = true, .proxy_pd_names = (char*[]){ @@ -950,8 +1119,69 @@ static const struct adsp_data sm8450_mpss_resource = { .ssctl_id = 0x12, }; +static const struct adsp_data sm8550_adsp_resource = { + .crash_reason_smem = 423, + .firmware_name = "adsp.mdt", + .dtb_firmware_name = "adsp_dtb.mdt", + .pas_id = 1, + .dtb_pas_id = 0x24, + .minidump_id = 5, + .auto_boot = true, + .proxy_pd_names = (char*[]){ + "lcx", + "lmx", + NULL + }, + .load_state = "adsp", + .ssr_name = "lpass", + .sysmon_name = "adsp", + .ssctl_id = 0x14, +}; + +static const struct adsp_data sm8550_cdsp_resource = { + .crash_reason_smem = 601, + .firmware_name = "cdsp.mdt", + .dtb_firmware_name = "cdsp_dtb.mdt", + .pas_id = 18, + .dtb_pas_id = 0x25, + .minidump_id = 7, + .auto_boot = true, + .proxy_pd_names = (char*[]){ + "cx", + "mxc", + "nsp", + NULL + }, + .load_state = "cdsp", + .ssr_name = "cdsp", + .sysmon_name = "cdsp", + .ssctl_id = 0x17, +}; + +static const struct adsp_data sm8550_mpss_resource = { + .crash_reason_smem = 421, + .firmware_name = "modem.mdt", + .dtb_firmware_name = "modem_dtb.mdt", + .pas_id = 4, + .dtb_pas_id = 0x26, + .minidump_id = 3, + .auto_boot = false, + .decrypt_shutdown = true, + .proxy_pd_names = (char*[]){ + "cx", + "mss", + NULL + }, + .load_state = "modem", + .ssr_name = "mpss", + .sysmon_name = "modem", + .ssctl_id = 0x12, + .region_assign_idx = 2, +}; + static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,msm8226-adsp-pil", .data = &adsp_resource_init}, + { .compatible = "qcom,msm8953-adsp-pil", .data = &msm8996_adsp_resource}, { .compatible = "qcom,msm8974-adsp-pil", .data = &adsp_resource_init}, { .compatible = "qcom,msm8996-adsp-pil", .data = &msm8996_adsp_resource}, { .compatible = "qcom,msm8996-slpi-pil", .data = &slpi_resource_init}, @@ -972,6 +1202,9 @@ static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,sdm845-adsp-pas", .data = &sdm845_adsp_resource_init}, { .compatible = "qcom,sdm845-cdsp-pas", .data = &sdm845_cdsp_resource_init}, { .compatible = "qcom,sdx55-mpss-pas", .data = &sdx55_mpss_resource}, + { .compatible = "qcom,sm6115-adsp-pas", .data = &adsp_resource_init}, + { .compatible = "qcom,sm6115-cdsp-pas", .data = &cdsp_resource_init}, + { .compatible = "qcom,sm6115-mpss-pas", .data = &sc8180x_mpss_resource}, { .compatible = "qcom,sm6350-adsp-pas", .data = &sm6350_adsp_resource}, { .compatible = "qcom,sm6350-cdsp-pas", .data = &sm6350_cdsp_resource}, { .compatible = "qcom,sm6350-mpss-pas", .data = &mpss_resource_init}, @@ -990,6 +1223,9 @@ static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,sm8450-cdsp-pas", .data = &sm8350_cdsp_resource}, { .compatible = "qcom,sm8450-slpi-pas", .data = &sm8350_slpi_resource}, { .compatible = "qcom,sm8450-mpss-pas", .data = &sm8450_mpss_resource}, + { .compatible = "qcom,sm8550-adsp-pas", .data = &sm8550_adsp_resource}, + { .compatible = "qcom,sm8550-cdsp-pas", .data = &sm8550_cdsp_resource}, + { .compatible = "qcom,sm8550-mpss-pas", .data = &sm8550_mpss_resource}, { }, }; MODULE_DEVICE_TABLE(of, adsp_of_match); diff --git a/drivers/remoteproc/qcom_sysmon.c b/drivers/remoteproc/qcom_sysmon.c index 85393d5eb005..746f56b4bafb 100644 --- a/drivers/remoteproc/qcom_sysmon.c +++ b/drivers/remoteproc/qcom_sysmon.c @@ -388,7 +388,7 @@ static void ssctl_send_event(struct qcom_sysmon *sysmon, } memset(&req, 0, sizeof(req)); - strlcpy(req.subsys_name, event->subsys_name, sizeof(req.subsys_name)); + strscpy(req.subsys_name, event->subsys_name, sizeof(req.subsys_name)); req.subsys_name_len = strlen(req.subsys_name); req.event = event->ssr_event; req.evt_driven_valid = true; diff --git a/drivers/remoteproc/qcom_wcnss.c b/drivers/remoteproc/qcom_wcnss.c index 68f37296b151..f599d5d5719d 100644 --- a/drivers/remoteproc/qcom_wcnss.c +++ b/drivers/remoteproc/qcom_wcnss.c @@ -141,6 +141,17 @@ static const struct wcnss_data pronto_v2_data = { .num_vregs = 1, }; +static const struct wcnss_data pronto_v3_data = { + .pmu_offset = 0x1004, + .spare_offset = 0x1088, + + .pd_names = { "mx", "cx" }, + .vregs = (struct wcnss_vreg_info[]) { + { "vddpx", 1800000, 1800000, 0 }, + }, + .num_vregs = 1, +}; + static int wcnss_load(struct rproc *rproc, const struct firmware *fw) { struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv; @@ -675,6 +686,7 @@ static const struct of_device_id wcnss_of_match[] = { { .compatible = "qcom,riva-pil", &riva_data }, { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data }, { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data }, + { .compatible = "qcom,pronto-v3-pil", &pronto_v3_data }, { }, }; MODULE_DEVICE_TABLE(of, wcnss_of_match); diff --git a/drivers/remoteproc/qcom_wcnss.h b/drivers/remoteproc/qcom_wcnss.h index 6d01ee6afa7f..cb4ce543e68f 100644 --- a/drivers/remoteproc/qcom_wcnss.h +++ b/drivers/remoteproc/qcom_wcnss.h @@ -5,8 +5,6 @@ struct qcom_iris; struct qcom_wcnss; -extern struct platform_driver qcom_iris_driver; - struct wcnss_vreg_info { const char * const name; int min_voltage; diff --git a/drivers/remoteproc/ti_k3_dsp_remoteproc.c b/drivers/remoteproc/ti_k3_dsp_remoteproc.c index eb9c64f7b9b4..ec626a37fef6 100644 --- a/drivers/remoteproc/ti_k3_dsp_remoteproc.c +++ b/drivers/remoteproc/ti_k3_dsp_remoteproc.c @@ -870,6 +870,10 @@ static const struct k3_dsp_mem_data c71_mems[] = { { .name = "l1dram", .dev_addr = 0xe00000 }, }; +static const struct k3_dsp_mem_data c7xv_mems[] = { + { .name = "l2sram", .dev_addr = 0x800000 }, +}; + static const struct k3_dsp_dev_data c66_data = { .mems = c66_mems, .num_mems = ARRAY_SIZE(c66_mems), @@ -884,10 +888,18 @@ static const struct k3_dsp_dev_data c71_data = { .uses_lreset = false, }; +static const struct k3_dsp_dev_data c7xv_data = { + .mems = c7xv_mems, + .num_mems = ARRAY_SIZE(c7xv_mems), + .boot_align_addr = SZ_2M, + .uses_lreset = false, +}; + static const struct of_device_id k3_dsp_of_match[] = { { .compatible = "ti,j721e-c66-dsp", .data = &c66_data, }, { .compatible = "ti,j721e-c71-dsp", .data = &c71_data, }, { .compatible = "ti,j721s2-c71-dsp", .data = &c71_data, }, + { .compatible = "ti,am62a-c7xv-dsp", .data = &c7xv_data, }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, k3_dsp_of_match); diff --git a/include/linux/remoteproc/pruss.h b/include/linux/remoteproc/pruss.h new file mode 100644 index 000000000000..039b50d58df2 --- /dev/null +++ b/include/linux/remoteproc/pruss.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * PRU-ICSS Subsystem user interfaces + * + * Copyright (C) 2015-2022 Texas Instruments Incorporated - http://www.ti.com + * Suman Anna <s-anna@ti.com> + */ + +#ifndef __LINUX_PRUSS_H +#define __LINUX_PRUSS_H + +#include <linux/device.h> +#include <linux/types.h> + +#define PRU_RPROC_DRVNAME "pru-rproc" + +/** + * enum pruss_pru_id - PRU core identifiers + * @PRUSS_PRU0: PRU Core 0. + * @PRUSS_PRU1: PRU Core 1. + * @PRUSS_NUM_PRUS: Total number of PRU Cores available. + * + */ + +enum pruss_pru_id { + PRUSS_PRU0 = 0, + PRUSS_PRU1, + PRUSS_NUM_PRUS, +}; + +/* + * enum pru_ctable_idx - Configurable Constant table index identifiers + */ +enum pru_ctable_idx { + PRU_C24 = 0, + PRU_C25, + PRU_C26, + PRU_C27, + PRU_C28, + PRU_C29, + PRU_C30, + PRU_C31, +}; + +struct device_node; +struct rproc; + +#if IS_ENABLED(CONFIG_PRU_REMOTEPROC) + +struct rproc *pru_rproc_get(struct device_node *np, int index, + enum pruss_pru_id *pru_id); +void pru_rproc_put(struct rproc *rproc); +int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr); + +#else + +static inline struct rproc * +pru_rproc_get(struct device_node *np, int index, enum pruss_pru_id *pru_id) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +static inline void pru_rproc_put(struct rproc *rproc) { } + +static inline int pru_rproc_set_ctable(struct rproc *rproc, + enum pru_ctable_idx c, u32 addr) +{ + return -EOPNOTSUPP; +} + +#endif /* CONFIG_PRU_REMOTEPROC */ + +static inline bool is_pru_rproc(struct device *dev) +{ + const char *drv_name = dev_driver_string(dev); + + if (strncmp(drv_name, PRU_RPROC_DRVNAME, sizeof(PRU_RPROC_DRVNAME))) + return false; + + return true; +} + +#endif /* __LINUX_PRUSS_H */ |