diff options
| author |   Jouni Högander <jouni.hogander@intel.com> | 2023-12-18 19:50:04 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2024-01-09 15:40:00 +0200 |
| commit | f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d (patch) | |
| tree | 82340e3cc127437d44815462abb99de817467ad1 | |
| parent | drm/i915/psr: Enable psr2 early transport as possible (diff) | |
| download | wireguard-linux-f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d.tar.xz wireguard-linux-f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d.zip | |
drm/i915/psr: Disable early transport by default
Early transport validation is currently incomplete. Due to this disable the
feature by default.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231218175004.52875-8-jouni.hogander@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 682ceae00710..dff21a5edeb7 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2842,6 +2842,9 @@ void intel_psr_init(struct intel_dp *intel_dp) else intel_dp->psr.source_support = true; + /* Disable early transport for now */ + intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE; + /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) /* For new platforms up to TGL let's respect VBT back again */ |