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| author |   Paul Hsieh <paul.hsieh@amd.com> | 2024-05-28 14:36:00 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-06-14 16:17:16 -0400 |
| commit | fc6d61ad1dc7dda7b32f1d1c08d0e6e372cda628 (patch) | |
| tree | 6786964f631911dce8f730a08604f54db3925ec1 | |
| parent | drm/amd/display: Change dram_clock_latency to 34us for dcn351 (diff) | |
| download | wireguard-linux-fc6d61ad1dc7dda7b32f1d1c08d0e6e372cda628.tar.xz wireguard-linux-fc6d61ad1dc7dda7b32f1d1c08d0e6e372cda628.zip | |
drm/amd/display: change dram_clock_latency to 34us for dcn35
[Why & How]
Current DRAM setting would cause underflow on customer platform.
Modify dram_clock_change_latency_us from 11.72 to 34.0 us as per recommendation from HW team
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 60f251cf973b..beed7adbbd43 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -177,7 +177,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { .urgent_latency_pixel_data_only_us = 4.0, .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, .urgent_latency_vm_data_only_us = 4.0, - .dram_clock_change_latency_us = 11.72, + .dram_clock_change_latency_us = 34.0, .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, |