diff options
| author |   Hugo Hu <hugo.hu@amd.com> | 2020-05-13 16:36:28 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-05-28 14:00:51 -0400 |
| commit | fd0293dd5b68a67a8731d54a6b334945e4e95757 (patch) | |
| tree | a07693c8845249a6dbf09c652f9fec39f5c821c2 | |
| parent | drm/amd/display: combine public interfaces into single header (diff) | |
| download | wireguard-linux-fd0293dd5b68a67a8731d54a6b334945e4e95757.tar.xz wireguard-linux-fd0293dd5b68a67a8731d54a6b334945e4e95757.zip | |
drm/amd/display: enable plane if container of plane_status changed
[why]
We hit an issue which driver reallocate a pipe from desktop bottom
pipe to video bottom pipe. In this case, driver need to re-enable
plane.
[how]
Enable plane if container of plane status changed.
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 223e314d26b4..13183bd7ea0f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1160,13 +1160,20 @@ void dcn20_pipe_control_lock( static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe) { + bool plane_state_update = false; new_pipe->update_flags.raw = 0; /* Exit on unchanged, unused pipe */ if (!old_pipe->plane_state && !new_pipe->plane_state) return; + + /* Detect plane state update */ + if (old_pipe->plane_state && new_pipe->plane_state + && (old_pipe->plane_state != new_pipe->plane_state)) { + plane_state_update = true; + } /* Detect pipe enable/disable */ - if (!old_pipe->plane_state && new_pipe->plane_state) { + if ((!old_pipe->plane_state && new_pipe->plane_state) || plane_state_update) { new_pipe->update_flags.bits.enable = 1; new_pipe->update_flags.bits.mpcc = 1; new_pipe->update_flags.bits.dppclk = 1; |