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| author |   Mark Rutland <mark.rutland@arm.com> | 2018-12-07 18:39:31 +0000 |
|---|---|---|
| committer |   Will Deacon <will.deacon@arm.com> | 2018-12-13 16:42:47 +0000 |
| commit | fbedc599e9b891a6756b1c9bc2eead02b02cce77 (patch) | |
| tree | 1b832edd542d8edec1cd1df8519a7291bef53bc1 /Documentation/arm64/booting.txt | |
| parent | arm64: ptr auth: Move per-thread keys from thread_info to thread_struct (diff) | |
| download | wireguard-linux-fbedc599e9b891a6756b1c9bc2eead02b02cce77.tar.xz wireguard-linux-fbedc599e9b891a6756b1c9bc2eead02b02cce77.zip | |
arm64: docs: document pointer authentication
Now that we've added code to support pointer authentication, add some
documentation so that people can figure out if/how to use it.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Cc: Andrew Jones <drjones@redhat.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/arm64/booting.txt')
| -rw-r--r-- | Documentation/arm64/booting.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt index 8d0df62c3fe0..8df9f4658d6f 100644 --- a/Documentation/arm64/booting.txt +++ b/Documentation/arm64/booting.txt @@ -205,6 +205,14 @@ Before jumping into the kernel, the following conditions must be met: ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0. - The DT or ACPI tables must describe a GICv2 interrupt controller. + For CPUs with pointer authentication functionality: + - If EL3 is present: + SCR_EL3.APK (bit 16) must be initialised to 0b1 + SCR_EL3.API (bit 17) must be initialised to 0b1 + - If the kernel is entered at EL1: + HCR_EL2.APK (bit 40) must be initialised to 0b1 + HCR_EL2.API (bit 41) must be initialised to 0b1 + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. |