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| author |   Conor Dooley <conor.dooley@microchip.com> | 2022-08-23 19:33:17 +0100 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-10-12 17:05:15 -0700 |
| commit | 826249942679a110353e71a1d92764fcf43e7cf7 (patch) | |
| tree | 1322298f75ef9393ad22ab05f5895cf35c12ae83 /Documentation/conf.py | |
| parent | Linux 6.0-rc1 (diff) | |
| download | wireguard-linux-826249942679a110353e71a1d92764fcf43e7cf7.tar.xz wireguard-linux-826249942679a110353e71a1d92764fcf43e7cf7.zip | |
dt-bindings: timer: sifive,clint: add legacy riscv compatible
While "real" hardware might not use the compatible string "riscv,clint0"
it is present in the driver & QEMU uses it for automatically generated
virt machine dtbs. To avoid dt-validate problems with QEMU produced
dtbs, such as the following, add it to the binding.
riscv-virt.dtb: clint@2000000: compatible:0: 'sifive,clint0' is not one of ['sifive,fu540-c000-clint', 'starfive,jh7100-clint', 'canaan,k210-clint']
Reported-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220823183319.3314940-2-mail@conchuod.ie
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation/conf.py')
0 files changed, 0 insertions, 0 deletions