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author | Conor Dooley <conor.dooley@microchip.com> | 2023-03-30 18:32:56 +0100 |
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committer | Rob Herring <robh@kernel.org> | 2023-04-04 12:12:13 -0500 |
commit | dc8ea9204b242cd93e63585396ac7d13f622802d (patch) | |
tree | 1073f0a5dc0669c08b65a4523185e386466aff4c /Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | |
parent | dt-bindings: timer: convert timer/amlogic,meson6-timer.txt to dt-schema (diff) | |
download | wireguard-linux-dc8ea9204b242cd93e63585396ac7d13f622802d.tar.xz wireguard-linux-dc8ea9204b242cd93e63585396ac7d13f622802d.zip |
dt-bindings: move cache controller bindings to a cache directory
There's a bunch of bindings for (mostly l2) cache controllers
scattered to the four winds, move them to a common directory.
I renamed the freescale l2cache.txt file, as while that might make sense
when the parent dir is fsl, it's confusing after the move.
The two Marvell bindings have had a "marvell," prefix added to match
their compatibles.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml deleted file mode 100644 index 38efcad56dbd..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ /dev/null @@ -1,65 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Last Level Cache Controller - -maintainers: - - Rishabh Bhatnagar <rishabhb@codeaurora.org> - - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> - -description: | - LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, - that can be shared by multiple clients. Clients here are different cores in the - SoC, the idea is to minimize the local caches at the clients and migrate to - common pool of memory. Cache memory is divided into partitions called slices - which are assigned to clients. Clients can query the slice details, activate - and deactivate them. - -properties: - compatible: - enum: - - qcom,sc7180-llcc - - qcom,sc7280-llcc - - qcom,sc8180x-llcc - - qcom,sc8280xp-llcc - - qcom,sdm845-llcc - - qcom,sm6350-llcc - - qcom,sm8150-llcc - - qcom,sm8250-llcc - - qcom,sm8350-llcc - - qcom,sm8450-llcc - - qcom,sm8550-llcc - - reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region - - reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base - - interrupts: - maxItems: 1 - -required: - - compatible - - reg - - reg-names - -additionalProperties: false - -examples: - - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; - }; |