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authorMichal Simek <michal.simek@amd.com>2023-05-16 15:51:08 +0200
committerMichal Simek <michal.simek@amd.com>2023-06-05 13:09:19 +0200
commitd5c421d24d7eca0a2c9708cf0b3fbc1e63f9136a (patch)
tree3f00fd7526f58daf595fe62a57684ad0ff19237b /Documentation/devicetree/bindings/gpio
parentarm64: xilinx: Use zynqmp prefix for SOM dt overlays (diff)
downloadwireguard-linux-d5c421d24d7eca0a2c9708cf0b3fbc1e63f9136a.tar.xz
wireguard-linux-d5c421d24d7eca0a2c9708cf0b3fbc1e63f9136a.zip
dt-bindings: xilinx: Switch xilinx.com emails to amd.com
@xilinx.com is still working but better to switch to new amd.com after AMD/Xilinx acquisition. Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Acked-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
Diffstat (limited to 'Documentation/devicetree/bindings/gpio')
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-zynq.yaml2
-rw-r--r--Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml2
-rw-r--r--Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml2
3 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
index 572e1718f501..5e2496379a3c 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
+++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq GPIO controller
maintainers:
- - Michal Simek <michal.simek@xilinx.com>
+ - Michal Simek <michal.simek@amd.com>
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
index f333ee2288e7..c1060e5fcef3 100644
--- a/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
+++ b/Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI GPIO controller
maintainers:
- - Neeli Srinivas <srinivas.neeli@xilinx.com>
+ - Neeli Srinivas <srinivas.neeli@amd.com>
description:
The AXI GPIO design provides a general purpose input/output interface
diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
index 31c0fc345903..18e61aff2185 100644
--- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
+++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
@@ -12,7 +12,7 @@ description:
PS_MODE). Every pin can be configured as input/output.
maintainers:
- - Piyush Mehta <piyush.mehta@xilinx.com>
+ - Piyush Mehta <piyush.mehta@amd.com>
properties:
compatible: