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| author |   Vignesh R <vigneshr@ti.com> | 2019-02-12 14:08:08 +0530 |
|---|---|---|
| committer |   Boris Brezillon <boris.brezillon@collabora.com> | 2019-02-13 15:13:21 +0100 |
| commit | 70b64604fef0fb6fbc3bf6fbd9cd90b73ab0dfa8 (patch) | |
| tree | 4d1754eba50fa7fa8b976b8ad3fc633866cdffdf /Documentation/devicetree/bindings/mtd | |
| parent | mtd: spi-nor: split s25fl128s into s25fl128s0 and s25fl128s1 (diff) | |
| download | wireguard-linux-70b64604fef0fb6fbc3bf6fbd9cd90b73ab0dfa8.tar.xz wireguard-linux-70b64604fef0fb6fbc3bf6fbd9cd90b73ab0dfa8.zip | |
dt-bindings: cadence-quadspi: Add new compatible for AM654 SoC
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence
QSPI controller but supports Octal IO(x8 data lines) and Double Data
Rate(DDR) mode. Add new compatible to support OSPI controller on TI's
AM654 SoCs.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Diffstat (limited to 'Documentation/devicetree/bindings/mtd')
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index bb2075df9b38..4345c3a6f530 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -4,6 +4,7 @@ Required properties: - compatible : should be one of the following: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". + For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the |