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authorSerge Semin <Sergey.Semin@baikalelectronics.ru>2022-11-13 22:12:49 +0300
committerLorenzo Pieralisi <lpieralisi@kernel.org>2022-11-23 16:01:54 +0100
commit12f7936c7a0e0c40069ff12ddfd091a29da6e77c (patch)
tree4aa6f7fbdf002a46e17a918c02aaded86a968cb3 /Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
parentdt-bindings: PCI: dwc: Apply generic schema for generic device only (diff)
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dt-bindings: PCI: dwc: Add max-functions EP property
In accordance with [1] the CX_NFUNC IP-core synthesize parameter is responsible for the number of physical functions to support in the EP mode. Its upper limit is 32. Let's use it to constrain the number of PCIe functions the DW PCIe EP DT-nodes can advertise. [1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint, Version 5.40a, March 2019, p. 887. Link: https://lore.kernel.org/r/20221113191301.5526-9-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml')
-rw-r--r--Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml4
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index d04001248b53..71dd19ae1060 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -41,6 +41,9 @@ properties:
items:
enum: [dbi, dbi2, config, atu, addr_space, link, atu_dma, appl]
+ max-functions:
+ maximum: 32
+
required:
- compatible
- reg
@@ -61,4 +64,5 @@ examples:
phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
max-link-speed = <3>;
+ max-functions = /bits/ 8 <4>;
};