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| author |   Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2022-11-13 22:12:47 +0300 |
|---|---|---|
| committer |   Lorenzo Pieralisi <lpieralisi@kernel.org> | 2022-11-23 16:01:54 +0100 |
| commit | eaa9d886528730bcd7213f0b22c8dd468460f495 (patch) | |
| tree | cca2e958aaf66694d41c405b05a376b7d1cf7bdb /Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | |
| parent | dt-bindings: PCI: dwc: Add phys/phy-names common properties (diff) | |
| download | wireguard-linux-eaa9d886528730bcd7213f0b22c8dd468460f495.tar.xz wireguard-linux-eaa9d886528730bcd7213f0b22c8dd468460f495.zip | |
dt-bindings: PCI: dwc: Add max-link-speed common property
In accordance with [1] DW PCIe controllers support up to Gen5 link speed.
Let's add the max-link-speed property upper bound to 5 then. The DT
bindings of the particular devices are expected to setup more strict
constraint on that parameter.
[1] Synopsys DesignWare Cores PCI Express Controller Databook, Version
5.40a, March 2019, p. 27
Link: https://lore.kernel.org/r/20221113191301.5526-7-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index dcd521aed213..fc3b5d4ac245 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -55,4 +55,6 @@ examples: phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>; phy-names = "pcie0", "pcie1", "pcie2", "pcie3"; + + max-link-speed = <3>; }; |