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| author |   Conor Dooley <conor.dooley@microchip.com> | 2023-03-30 18:32:56 +0100 |
|---|---|---|
| committer |   Rob Herring <robh@kernel.org> | 2023-04-04 12:12:13 -0500 |
| commit | dc8ea9204b242cd93e63585396ac7d13f622802d (patch) | |
| tree | 1073f0a5dc0669c08b65a4523185e386466aff4c /Documentation/devicetree/bindings/powerpc | |
| parent | dt-bindings: timer: convert timer/amlogic,meson6-timer.txt to dt-schema (diff) | |
| download | wireguard-linux-dc8ea9204b242cd93e63585396ac7d13f622802d.tar.xz wireguard-linux-dc8ea9204b242cd93e63585396ac7d13f622802d.zip | |
dt-bindings: move cache controller bindings to a cache directory
There's a bunch of bindings for (mostly l2) cache controllers
scattered to the four winds, move them to a common directory.
I renamed the freescale l2cache.txt file, as while that might make sense
when the parent dir is fsl, it's confusing after the move.
The two Marvell bindings have had a "marvell," prefix added to match
their compatibles.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230330173255.109731-1-conor@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc')
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt deleted file mode 100644 index 22ad012660e9..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt +++ /dev/null @@ -1,55 +0,0 @@ -Freescale L2 Cache Controller - -L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms. -The cache bindings explained below are Devicetree Specification compliant - -Required Properties: - -- compatible : Should include one of the following: - "fsl,b4420-l2-cache-controller" - "fsl,b4860-l2-cache-controller" - "fsl,bsc9131-l2-cache-controller" - "fsl,bsc9132-l2-cache-controller" - "fsl,c293-l2-cache-controller" - "fsl,mpc8536-l2-cache-controller" - "fsl,mpc8540-l2-cache-controller" - "fsl,mpc8541-l2-cache-controller" - "fsl,mpc8544-l2-cache-controller" - "fsl,mpc8548-l2-cache-controller" - "fsl,mpc8555-l2-cache-controller" - "fsl,mpc8560-l2-cache-controller" - "fsl,mpc8568-l2-cache-controller" - "fsl,mpc8569-l2-cache-controller" - "fsl,mpc8572-l2-cache-controller" - "fsl,p1010-l2-cache-controller" - "fsl,p1011-l2-cache-controller" - "fsl,p1012-l2-cache-controller" - "fsl,p1013-l2-cache-controller" - "fsl,p1014-l2-cache-controller" - "fsl,p1015-l2-cache-controller" - "fsl,p1016-l2-cache-controller" - "fsl,p1020-l2-cache-controller" - "fsl,p1021-l2-cache-controller" - "fsl,p1022-l2-cache-controller" - "fsl,p1023-l2-cache-controller" - "fsl,p1024-l2-cache-controller" - "fsl,p1025-l2-cache-controller" - "fsl,p2010-l2-cache-controller" - "fsl,p2020-l2-cache-controller" - "fsl,t2080-l2-cache-controller" - "fsl,t4240-l2-cache-controller" - and "cache". -- reg : Address and size of L2 cache controller registers -- cache-size : Size of the entire L2 cache -- interrupts : Error interrupt of L2 controller -- cache-line-size : Size of L2 cache lines - -Example: - - L2: l2-cache-controller@20000 { - compatible = "fsl,bsc9132-l2-cache-controller", "cache"; - reg = <0x20000 0x1000>; - cache-line-size = <32>; // 32 bytes - cache-size = <0x40000>; // L2,256K - interrupts = <16 2 1 0>; - }; |