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author | Thomas Zimmermann <tzimmermann@suse.de> | 2020-04-17 08:12:22 +0200 |
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committer | Thomas Zimmermann <tzimmermann@suse.de> | 2020-04-17 08:12:22 +0200 |
commit | 08d99b2c23dfa84ca5b5e5c194062a0550888b71 (patch) | |
tree | f4cf81ba52b375bbafd3b7ee2603b3a4cae7fe30 /Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml | |
parent | drm: Don't free a struct never allocated by drm_gem_fb_init() (diff) | |
parent | Linux 5.7-rc1 (diff) | |
download | wireguard-linux-08d99b2c23dfa84ca5b5e5c194062a0550888b71.tar.xz wireguard-linux-08d99b2c23dfa84ca5b5e5c194062a0550888b71.zip |
Merge drm/drm-next into drm-misc-next
Backmerging required to pull topic/phy-compliance.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Diffstat (limited to 'Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml new file mode 100644 index 000000000000..09a30300850c --- /dev/null +++ b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier UART controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + const: socionext,uniphier-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + auto-flow-control: + description: enable automatic flow control support. + $ref: /schemas/types.yaml#/definitions/flag + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + aliases { + serial0 = &serial0; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + }; |