Merge tag 'mtd/for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD updates from Miquel Raynal:
 "MTD core:
   - drop inactive maintainers, update the repositories and add IRC
     channel
   - debugfs functions improvements
   - initialize more structure parameters
   - misc fixes reported by robots

  MTD devices:
   - spear_smi: Fixed Write Burst mode
   - new Intel IXP4xx flash probing hook

  Raw NAND core:
   - useless extra checks dropped
   - update the detection of the bad block markers position

  Raw NAND controller drivers:
   - Cadence: new driver
   - Brcmnand: support for flash-dma v0 + fixes
   - Denali: drop support for the legacy controller/chip DT representation
   - superfluous dev_err() calls removed

  SPI NOR core changes:
   - introduce 'struct spi_nor_controller_ops'
   - clean the Register Operations methods
   - use dev_dbg insted of dev_err for low level info
   - fix retlen handling in sst_write()
   - fix silent truncations in spi_nor_read and spi_nor_read_raw()
   - fix the clearing of QE bit on lock()/unlock()
   - rework the disabling of the block write protection
   - rework the Quad Enable methods
   - make sure nor->spimem and nor->controller_ops are mutually exclusive
   - set default Quad Enable method for ISSI flashes
   - add support for few flashes

  SPI NOR controller drivers changes:
   - intel-spi:
      - support chips without software sequencer
      - add support for Intel Cannon Lake and Intel Comet Lake-H flashes

  CFI core changes:
   - code cleanups related useless initializers and coding style issues
   - fix for a possible double free problem in cfi_cmdset_0002
   - improved HyperFlash error reporting and handling in cfi_cmdset_0002 core"

* tag 'mtd/for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (73 commits)
  mtd: devices: fix mchp23k256 read and write
  mtd: no need to check return value of debugfs_create functions
  mtd: spi-nor: Set default Quad Enable method for ISSI flashes
  mtd: spi-nor: Add support for is25wp256
  mtd: spi-nor: Add support for w25q256jw
  mtd: spi-nor: Move condition to avoid a NULL check
  mtd: spi-nor: Make sure nor->spimem and nor->controller_ops are mutually exclusive
  mtd: spi-nor: Rename Quad Enable methods
  mtd: spi-nor: Merge spansion Quad Enable methods
  mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1
  mtd: spi-nor: Extend the SR Read Back test
  mtd: spi-nor: Rework the disabling of block write protection
  mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()
  mtd: cfi_cmdset_0002: fix delayed error detection on HyperFlash
  mtd: cfi_cmdset_0002: only check errors when ready in cfi_check_err_status()
  mtd: cfi_cmdset_0002: don't free cfi->cfiq in error path of cfi_amdstd_setup()
  mtd: cfi_cmdset_*: kill useless 'ret' variable initializers
  mtd: cfi_util: use DIV_ROUND_UP() in cfi_udelay()
  mtd: spi-nor: Print debug message when the read back test fails
  mtd: spi-nor: Check all the bits written, not just the BP ones
  ...

2 files changed, 75 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
new file mode 100644
index 000000000000..f3893c4d3c6a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt
@@ -0,0 +1,53 @@
+* Cadence NAND controller
+
+Required properties:
+  - compatible : "cdns,hp-nfc"
+  - reg : Contains two entries, each of which is a tuple consisting of a
+	  physical address and length. The first entry is the address and
+	  length of the controller register set. The second entry is the
+	  address and length of the Slave DMA data port.
+  - reg-names: should contain "reg" and "sdma"
+  - #address-cells: should be 1. The cell encodes the chip select connection.
+  - #size-cells : should be 0.
+  - interrupts : The interrupt number.
+  - clocks: phandle of the controller core clock (nf_clk).
+
+Optional properties:
+  - dmas: shall reference DMA channel associated to the NAND controller
+  - cdns,board-delay-ps : Estimated Board delay. The value includes the total
+    round trip delay for the signals and is used for deciding on values
+    associated with data read capture. The example formula for SDR mode is
+    the following:
+    board delay = RE#PAD delay + PCB trace to device + PCB trace from device
+    + DQ PAD delay
+
+Child nodes represent the available NAND chips.
+
+Required properties of NAND chips:
+  - reg: shall contain the native Chip Select ids from 0 to max supported by
+    the cadence nand flash controller
+
+See Documentation/devicetree/bindings/mtd/nand.txt for more details on
+generic bindings.
+
+Example:
+
+nand_controller: nand-controller@60000000 {
+	  compatible = "cdns,hp-nfc";
+	  #address-cells = <1>;
+	  #size-cells = <0>;
+	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
+	  reg-names = "reg", "sdma";
+	  clocks = <&nf_clk>;
+	  cdns,board-delay-ps = <4830>;
+	  interrupts = <2 0>;
+	  nand@0 {
+	      reg = <0>;
+	      label = "nand-1";
+	  };
+	  nand@1 {
+	      reg = <1>;
+	      label = "nand-2";
+	  };
+
+};
diff --git a/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt
new file mode 100644
index 000000000000..4bdcb92ae381
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt
@@ -0,0 +1,22 @@
+Flash device on Intel IXP4xx SoC
+
+This flash is regular CFI compatible (Intel or AMD extended) flash chips with
+specific big-endian or mixed-endian memory access pattern.
+
+Required properties:
+- compatible : must be "intel,ixp4xx-flash", "cfi-flash";
+- reg : memory address for the flash chip
+- bank-width : width in bytes of flash interface, should be <2>
+
+For the rest of the properties, see mtd-physmap.txt.
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Example:
+
+flash@50000000 {
+	compatible = "intel,ixp4xx-flash", "cfi-flash";
+	reg = <0x50000000 0x01000000>;
+	bank-width = <2>;
+};