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author | Will Deacon <will@kernel.org> | 2022-07-25 10:56:40 +0100 |
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committer | Will Deacon <will@kernel.org> | 2022-07-25 10:56:40 +0100 |
commit | b7c47fd771aa19d00e093742be2672b8d963c389 (patch) | |
tree | f12de817697104ad390ca801fcc43d3df17756d8 /Documentation | |
parent | Merge branch 'for-next/irqflags-nmi' into for-next/core (diff) | |
parent | arm64: kcsan: Support detecting more missing memory barriers (diff) | |
download | wireguard-linux-b7c47fd771aa19d00e093742be2672b8d963c389.tar.xz wireguard-linux-b7c47fd771aa19d00e093742be2672b8d963c389.zip |
Merge branch 'for-next/kcsan' into for-next/core
* for-next/kcsan:
arm64: kcsan: Support detecting more missing memory barriers
asm-generic: Add memory barrier dma_mb()
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/memory-barriers.txt | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index b12df9137e1c..832b5d36e279 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -1894,6 +1894,7 @@ There are some more advanced barrier functions: (*) dma_wmb(); (*) dma_rmb(); + (*) dma_mb(); These are for use with consistent memory to guarantee the ordering of writes or reads of shared memory accessible to both the CPU and a @@ -1925,11 +1926,11 @@ There are some more advanced barrier functions: The dma_rmb() allows us guarantee the device has released ownership before we read the data from the descriptor, and the dma_wmb() allows us to guarantee the data is written to the descriptor before the device - can see it now has ownership. Note that, when using writel(), a prior - wmb() is not needed to guarantee that the cache coherent memory writes - have completed before writing to the MMIO region. The cheaper - writel_relaxed() does not provide this guarantee and must not be used - here. + can see it now has ownership. The dma_mb() implies both a dma_rmb() and + a dma_wmb(). Note that, when using writel(), a prior wmb() is not needed + to guarantee that the cache coherent memory writes have completed before + writing to the MMIO region. The cheaper writel_relaxed() does not provide + this guarantee and must not be used here. See the subsection "Kernel I/O barrier effects" for more information on relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for |