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authorArnd Bergmann <arnd@arndb.de>2022-07-01 16:11:58 +0200
committerArnd Bergmann <arnd@arndb.de>2022-07-01 16:11:59 +0200
commit3966af40559dd690ff42fdea8f40c1f647579d49 (patch)
tree493d52ca475fbd07b449d02ee3de8d8dc2aa2e50 /arch/arm/boot/dts/Makefile
parentMerge tag 'renesas-dt-bindings-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt (diff)
parentarm64: dts: altera: socfpga_stratix10: move clocks out of soc node (diff)
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Merge tag 'socfpga_dts_updates_for_v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA dts updates for v5.20 - Clean up the Mercury++ AA1 dts - Add support the Google Chameleon v3 board - Add defined GIC interrupt type for Agilex ECC - Fix coding style around Stratix10 QSPI dts entry - Add support for Stratix10 SW Virtual platform - Move clocks entry out of the Stratix10 soc node * tag 'socfpga_dts_updates_for_v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: altera: socfpga_stratix10: move clocks out of soc node arm64: dts: Add support for Stratix 10 Software Virtual Platform dt-bindings: altera: document Stratix 10 SWVP compatibles arm64: dts: altera: adjust whitespace around '=' arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC dt-bindings: altera: Add Chameleon v3 board ARM: dts: socfpga: Add Google Chameleon v3 devicetree ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi Link: https://lore.kernel.org/r/20220626004437.1224820-1-dinguyen@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/Makefile')
-rw-r--r--arch/arm/boot/dts/Makefile2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5112f493f494..fff06ce4ad70 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1148,7 +1148,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
s5pv210-torbreck.dtb
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
- socfpga_arria10_mercury_aa1.dtb \
+ socfpga_arria10_chameleonv3.dtb \
socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \