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authorTony Lindgren <tony@atomide.com>2021-01-18 10:03:24 +0200
committerTony Lindgren <tony@atomide.com>2021-01-18 10:03:24 +0200
commit87ab16b644f33620db395c1f569b0fca8768161a (patch)
tree31764e1de6544ddcac5a98371c0d36e7e9e36d26 /arch/arm/boot/dts/am33xx-l4.dtsi
parentLinux 5.11-rc1 (diff)
parentARM: dts: dra71-evm: mark ldo0 regulator as always on (diff)
downloadwireguard-linux-87ab16b644f33620db395c1f569b0fca8768161a.tar.xz
wireguard-linux-87ab16b644f33620db395c1f569b0fca8768161a.zip
Merge tag 'omap-for-v5.11/dt-late-signed' into omap-for-v5.12-dt
Late devicetree changes for omaps for v5.11 merge window Here are few more late changes that would be nice to get into v5.11: - More updates to use cpsw switchdev driver - Enable gta04 PMIC power management - Updates for dra7 for ECC support, 1.8GHz speed and keep the ldo0 regulator always on as specified in the data manual
Diffstat (limited to 'arch/arm/boot/dts/am33xx-l4.dtsi')
-rw-r--r--arch/arm/boot/dts/am33xx-l4.dtsi49
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index 78088506d25b..1fb22088caeb 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -765,6 +765,55 @@
phys = <&phy_gmii_sel 2 1>;
};
};
+
+ mac_sw: switch@0 {
+ compatible = "ti,am335x-cpsw-switch", "ti,cpsw-switch";
+ reg = <0x0 0x4000>;
+ ranges = <0 0 0x4000>;
+ clocks = <&cpsw_125mhz_gclk>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ syscon = <&scm_conf>;
+ status = "disabled";
+
+ interrupts = <40 41 42 43>;
+ interrupt-names = "rx_thresh", "rx", "tx", "misc";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 1 1>;
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ label = "port2";
+ mac-address = [ 00 00 00 00 00 00 ];
+ phys = <&phy_gmii_sel 2 1>;
+ };
+ };
+
+ davinci_mdio_sw: mdio@1000 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ clocks = <&cpsw_125mhz_gclk>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ reg = <0x1000 0x100>;
+ };
+
+ cpts {
+ clocks = <&cpsw_cpts_rft_clk>;
+ clock-names = "cpts";
+ };
+ };
};
target-module@180000 { /* 0x4a180000, ap 5 10.0 */