diff options
| author |   Chris Brandt <chris.brandt@renesas.com> | 2017-01-25 15:28:10 -0500 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-03-06 10:06:49 +0100 |
| commit | 3d2abda02ad2d06d5f22de7f6b0f39126670bc48 (patch) | |
| tree | 5adaf6511469fdb96bbea9dd6fbf9ae5b62a1123 /arch/arm/boot/dts/r7s72100.dtsi | |
| parent | Linux 4.11-rc1 (diff) | |
| download | wireguard-linux-3d2abda02ad2d06d5f22de7f6b0f39126670bc48.tar.xz wireguard-linux-3d2abda02ad2d06d5f22de7f6b0f39126670bc48.zip | |
ARM: dts: r7s72100: update sdhi clock bindings
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r7s72100.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r7s72100.dtsi | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index b8aa256bd515..614ba79a9774 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -162,9 +162,12 @@ #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0xfcfe0444 4>; - clocks = <&p1_clk>, <&p1_clk>; - clock-indices = <R7S72100_CLK_SDHI1 R7S72100_CLK_SDHI0>; - clock-output-names = "sdhi1", "sdhi0"; + clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>; + clock-indices = < + R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01 + R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11 + >; + clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11"; }; }; @@ -488,7 +491,9 @@ GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp12_clks R7S72100_CLK_SDHI0>; + clocks = <&mstp12_clks R7S72100_CLK_SDHI00>, + <&mstp12_clks R7S72100_CLK_SDHI01>; + clock-names = "core", "cd"; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -501,7 +506,9 @@ GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp12_clks R7S72100_CLK_SDHI1>; + clocks = <&mstp12_clks R7S72100_CLK_SDHI10>, + <&mstp12_clks R7S72100_CLK_SDHI11>; + clock-names = "core", "cd"; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; |