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| author |   Chris Brandt <chris.brandt@renesas.com> | 2017-01-23 08:55:18 -0500 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-01-24 13:25:04 +0100 |
| commit | cfddd3db08f619bf0c1764b3103caedb6793bc48 (patch) | |
| tree | 58eb0c7e3becb6bd369dc3e63232186e4fc0d6df /arch/arm/boot/dts/r7s72100.dtsi | |
| parent | ARM: dts: r8a7745: Link ARM GIC to clock and clock domain (diff) | |
| download | wireguard-linux-cfddd3db08f619bf0c1764b3103caedb6793bc48.tar.xz wireguard-linux-cfddd3db08f619bf0c1764b3103caedb6793bc48.zip | |
ARM: dts: r7s72100: add ostm clock to device tree
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r7s72100.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r7s72100.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 3dd427d68c83..d5946df29222 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -108,6 +108,15 @@ clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; }; + mstp5_clks: mstp5_clks@fcfe0428 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0428 4>; + clocks = <&p0_clk>, <&p0_clk>; + clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>; + clock-output-names = "ostm0", "ostm1"; + }; + mstp7_clks: mstp7_clks@fcfe0430 { #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; |