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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 11:35:05 +0200 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 11:52:23 +0200 |
| commit | f20d89ac0fefad2465e6ce6d64e9ff82e33889dd (patch) | |
| tree | bf4bf467f3ed9586dd67b5a84ba09aa781b9a8a8 /arch/arm/boot/dts/r7s72100.dtsi | |
| parent | dt-bindings: clk: r7s72100: Add missing I and G clocks (diff) | |
| download | wireguard-linux-f20d89ac0fefad2465e6ce6d64e9ff82e33889dd.tar.xz wireguard-linux-f20d89ac0fefad2465e6ce6d64e9ff82e33889dd.zip | |
ARM: dts: r7s72100: Add clock for CA9 CPU core
Improve hardware description by adding a clock property to the device
node corresponding to the CA9 CPU core.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r7s72100.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r7s72100.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 4ed12a4d9d51..ab9645a42eca 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -203,6 +203,7 @@ compatible = "arm,cortex-a9"; reg = <0>; clock-frequency = <400000000>; + clocks = <&cpg_clocks R7S72100_CLK_I>; next-level-cache = <&L2>; }; }; |