diff options
| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2022-09-02 07:27:52 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-09-09 12:17:13 +0200 |
| commit | 5b8adc815b80eb66d1a028ec7ce0d56ce6c7a81a (patch) | |
| tree | 2a6693dc83d143cd2a413a2e35d90312023f3502 /arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | |
| parent | ARM: dts: r9a06g032: Add CAN{0,1} nodes (diff) | |
| download | wireguard-linux-5b8adc815b80eb66d1a028ec7ce0d56ce6c7a81a.tar.xz wireguard-linux-5b8adc815b80eb66d1a028ec7ce0d56ce6c7a81a.zip | |
ARM: dts: r9a06g032-rzn1d400-db: Enable CAN1
The CN10/CN11 on RZ/N1-EB board are headers to add jumpers to select which
CAN interface to route to the real CAN connector J16.
For a normal use case either we need to wire CAN1 or CAN2, but not both.
This patch enables CAN1 and disables CAN2 by default assuming CN10/CN11
is wired for CAN1.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220902062752.56841-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts')
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts index 4bf813335e21..c18bbd7141c4 100644 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -26,6 +26,22 @@ }; }; +&can0 { + pinctrl-0 = <&pins_can0>; + pinctrl-names = "default"; + + /* Assuming CN10/CN11 are wired for CAN1 */ + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&pins_can1>; + pinctrl-names = "default"; + + /* Please only enable can0 or can1, depending on CN10/CN11 */ + /* status = "okay"; */ +}; + ð_miic { status = "okay"; renesas,miic-switch-portin = <MIIC_GMAC2_PORT>; @@ -52,6 +68,18 @@ }; &pinctrl{ + pins_can0: pins_can0 { + pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */ + <RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */ + drive-strength = <6>; + }; + + pins_can1: pins_can1 { + pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>, /* CAN1_TXD */ + <RZN1_PINMUX(110, RZN1_FUNC_CAN)>; /* CAN1_RXD */ + drive-strength = <6>; + }; + pins_eth3: pins_eth3 { pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>, |