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| author |   Herve Codina <herve.codina@bootlin.com> | 2022-04-22 14:08:47 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-28 16:50:51 +0200 |
| commit | ed66b37f916ee23b308c3f50288131d51a2682e9 (patch) | |
| tree | 1026cd97b427671a08bfa4674119dad8822a515b /arch/arm/boot/dts/r9a06g032.dtsi | |
| parent | ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer node (diff) | |
| download | wireguard-linux-ed66b37f916ee23b308c3f50288131d51a2682e9.tar.xz wireguard-linux-ed66b37f916ee23b308c3f50288131d51a2682e9.zip | |
ARM: dts: r9a06g032: Add missing '#power-domain-cells'
Without '#power-domain-cells' property, power-domains cannot
be used. This property is noted required in the device-tree
binding.
Add '#power-domain-cells' as needed.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Link: https://lore.kernel.org/r/20220422120850.769480-6-herve.codina@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm/boot/dts/r9a06g032.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r9a06g032.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 2257706ce84f..cd9dc815089f 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -87,6 +87,7 @@ reg = <0x4000c000 0x1000>; status = "okay"; #clock-cells = <1>; + #power-domain-cells = <0>; clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>, <&ext_rgmii_ref>; |