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| author |   Claudiu Beznea <claudiu.beznea@microchip.com> | 2020-06-10 12:05:36 +0300 |
|---|---|---|
| committer |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2020-06-26 22:40:22 +0200 |
| commit | 5f6b33f463468b9595eebfed142756ba13ea2b60 (patch) | |
| tree | 297040d65655cfc2a555e41c0a142c9c4ec2b668 /arch/arm/boot/dts/sam9x60.dtsi | |
| parent | dt-bindings: rtc: add microchip,sam9x60-rtt (diff) | |
| download | wireguard-linux-5f6b33f463468b9595eebfed142756ba13ea2b60.tar.xz wireguard-linux-5f6b33f463468b9595eebfed142756ba13ea2b60.zip | |
ARM: dts: sam9x60: add rtt
Add RTT. Allong with it enable GBPR as it is requested by RTT.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/1591779936-18577-4-git-send-email-claudiu.beznea@microchip.com
Diffstat (limited to 'arch/arm/boot/dts/sam9x60.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sam9x60.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 6763423d64b8..d10843da4a85 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -661,6 +661,13 @@ status = "disabled"; }; + rtt: rtt@fffffe20 { + compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; + reg = <0xfffffe20 0x20>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k 0>; + }; + pit: timer@fffffe40 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe40 0x10>; |