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author | 2021-12-08 11:33:16 +0100 | |
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committer | 2022-02-07 09:52:57 +0100 | |
commit | b380a2d1890ad26574590e80789a58886a3a7f6b (patch) | |
tree | b59a377e381936bfcef9102dd2593e21156c5714 /arch/arm/boot/dts/stm32f429.dtsi | |
parent | ARM: dts: stm32: remove some timer duplicate unit-address on stm32f4 series (diff) | |
download | wireguard-linux-b380a2d1890ad26574590e80789a58886a3a7f6b.tar.xz wireguard-linux-b380a2d1890ad26574590e80789a58886a3a7f6b.zip |
ARM: dts: stm32: remove timer5 duplicate unit-address on stm32f4 series
Remove the following warnings seen when building with W=1.
Warning (unique_unit_address): /soc/timer@40000c00: duplicate unit-address
(also used in node /soc/timers@40000c00)
This approach is based on some discussions[1], to restructure the dtsi
and dts files.
Timer5 is enabled by default on stm32f4 series, to act as clockevent. In
order to get rid of the W=1 warning, and be compliant with dt-schemas
(e.g. dtbs_check):
- In stm32f429.dtsi:
. Keep the more complete timers5 description
. Remove the most simple timer5 node that is duplicate
- In each board:
. adopt "st,stm32-timer" compatible for timers5, also add the interrupt
. use /delete-property/ and /delete-node/ so the it matches the
clockevent bindings
Note: all this is done in one shot (e.g. not split) to keep clockevent
functionality.
[1] https://lore.kernel.org/linux-arm-kernel/Yaf4jiZIp8+ndaXs@robh.at.kernel.org/
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Diffstat (limited to 'arch/arm/boot/dts/stm32f429.dtsi')
-rw-r--r-- | arch/arm/boot/dts/stm32f429.dtsi | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index f21b3227d107..172334601faf 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -159,13 +159,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; |