diff options
| author |   Marek Vasut <marex@denx.de> | 2020-08-22 22:34:25 +0200 |
|---|---|---|
| committer |   Alexandre Torgue <alexandre.torgue@st.com> | 2020-09-23 18:37:02 +0200 |
| commit | 3c5c0eee95ece9a73969a94832093be8892cd4c1 (patch) | |
| tree | b7d5a937f02c0117884160f0d8cac1763693a5cf /arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | |
| parent | ARM: dts: stm32: Swap PHY reset GPIO and TSC2004 IRQ on DHCOM SOM (diff) | |
| download | wireguard-linux-3c5c0eee95ece9a73969a94832093be8892cd4c1.tar.xz wireguard-linux-3c5c0eee95ece9a73969a94832093be8892cd4c1.zip | |
ARM: dts: stm32: Enable RTS/CTS for DH AV96 UART7
The DH AV96 has RTS/CTS lines available on UART7, describe them in DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Diffstat (limited to 'arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 905cd7bb98cf..ec02cee1dd9b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -351,6 +351,7 @@ label = "LS-UART0"; pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; status = "okay"; }; |