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| author |   Dmitry Osipenko <digetx@gmail.com> | 2021-12-01 02:23:43 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2021-12-16 14:23:17 +0100 |
| commit | 83b7f0b8aeab4fc8271392fd32164efb7b3f55e9 (patch) | |
| tree | 8f687f28265d496e117b0c3f9f3f56c4ca13af60 /arch/arm/boot/dts/tegra20-tamonten.dtsi | |
| parent | ARM: tegra: Add 500 MHz entry to Tegra30 memory OPP table (diff) | |
| download | wireguard-linux-83b7f0b8aeab4fc8271392fd32164efb7b3f55e9.tar.xz wireguard-linux-83b7f0b8aeab4fc8271392fd32164efb7b3f55e9.zip | |
ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra20 SoC.
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-tamonten.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 2ad56f84bb62..de39c5465c0a 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -357,7 +357,7 @@ regulator-always-on; }; - sm0 { + vdd_core: sm0 { regulator-name = "vdd_sys_sm0,vdd_core"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -477,6 +477,7 @@ nvidia,core-pwr-good-time = <3845 3845>; nvidia,core-pwr-off-time = <3875>; nvidia,sys-clock-req-active-high; + core-supply = <&vdd_core>; }; pcie@80003000 { |