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| author |   Dmitry Osipenko <digetx@gmail.com> | 2020-08-23 17:47:25 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2020-09-17 18:09:40 +0200 |
| commit | 17110cbbef701b56136aabaaab5652b9ea4618a0 (patch) | |
| tree | 96a7359627c94d4b90f6fa6c9e639048a586096e /arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | |
| parent | ARM: tegra: acer-a500: Use PLLC for WiFi MMC clock parent (diff) | |
| download | wireguard-linux-17110cbbef701b56136aabaaab5652b9ea4618a0.tar.xz wireguard-linux-17110cbbef701b56136aabaaab5652b9ea4618a0.zip | |
ARM: tegra: nexus7: Use PLLC for WiFi MMC clock parent
The default parent for all MMCs is PLLP, which is running at 408 MHz on
Tegra30 and 50 MHz clock can't be derived from PLLP. The maximum SDIO
clock rate is 50 MHz, but this rate isn't achievable using PLLP.
Let's switch the WiFi MMC clock parent to PLLC in order to get true 50
MHz. This patch doesn't fix any problems, it's just a minor improvement.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 9999e1afd465..bca77ee33c74 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -945,6 +945,11 @@ #address-cells = <1>; #size-cells = <0>; + assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; keep-power-in-suspend; bus-width = <4>; non-removable; |