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| author |   Tomer Maimon <tmaimon77@gmail.com> | 2022-07-17 12:15:59 +0300 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2022-07-19 15:41:02 +0200 |
| commit | 8f73a173430b6e5f2968c73f61bbcca4701f9a42 (patch) | |
| tree | 011e74d47b2980f72cef2fd3384af90389b7d365 /arch/arm/boot/dts | |
| parent | dt-bindings: reset: npcm: add GCR syscon property (diff) | |
| download | wireguard-linux-8f73a173430b6e5f2968c73f61bbcca4701f9a42.tar.xz wireguard-linux-8f73a173430b6e5f2968c73f61bbcca4701f9a42.zip | |
ARM: dts: nuvoton: add reset syscon property
Add nuvoton,sysgcr syscon property to the reset node to handle the general
control registers.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts')
| -rw-r--r-- | arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index 3696980a3da1..8a2f29016291 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -110,6 +110,7 @@ compatible = "nuvoton,npcm750-reset"; reg = <0xf0801000 0x70>; #reset-cells = <2>; + nuvoton,sysgcr = <&gcr>; }; clk: clock-controller@f0801000 { |