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| author |   Michal Marek <mmarek@suse.cz> | 2010-08-20 13:53:08 +0200 |
|---|---|---|
| committer | Michal Marek <mmarek@suse.cz> | 2010-08-20 13:53:08 +0200 |
| commit | e981b060767b3c4ac9393ad8d2558d648e35dfcb (patch) | |
| tree | 9c05eaec3072be3645dda61d35085d152b9d5954 /arch/arm/include/asm/cache.h | |
| parent | fixes for using make 3.82 (diff) | |
| parent | Linux 2.6.36-rc1 (diff) | |
| download | wireguard-linux-e981b060767b3c4ac9393ad8d2558d648e35dfcb.tar.xz wireguard-linux-e981b060767b3c4ac9393ad8d2558d648e35dfcb.zip | |
Merge commit 'v2.6.36-rc1' into kbuild/rc-fixes
Diffstat (limited to 'arch/arm/include/asm/cache.h')
| -rw-r--r-- | arch/arm/include/asm/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 66c160b8547f..9d6122096fbe 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -14,7 +14,7 @@ * cache before the transfer is done, causing old data to be seen by * the CPU. */ -#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES /* * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. |