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| author |   Vladimir Murzin <vladimir.murzin@arm.com> | 2019-01-25 15:18:37 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@armlinux.org.uk> | 2019-02-01 21:44:19 +0000 |
| commit | 72cd4064fccaae15ab84d40d4be23667402df4ed (patch) | |
| tree | dbd4813fa104ed4e0359e5a546acee47fb5ef613 /arch/arm/kernel/entry-header.S | |
| parent | ARM: 8829/1: spinlock: use unified assembler language syntax (diff) | |
| download | wireguard-linux-72cd4064fccaae15ab84d40d4be23667402df4ed.tar.xz wireguard-linux-72cd4064fccaae15ab84d40d4be23667402df4ed.zip | |
ARM: 8830/1: NOMMU: Toggle only bits in EXC_RETURN we are really care of
ARMv8M introduces support for Security extension to M class, among
other things it affects exception handling, especially, encoding of
EXC_RETURN.
The new bits have been added:
Bit [6] Secure or Non-secure stack
Bit [5] Default callee register stacking
Bit [0] Exception Secure
which conflicts with hard-coded value of EXC_RETURN:
In fact, we only care of few bits:
Bit [3] Mode (0 - Handler, 1 - Thread)
Bit [2] Stack pointer selection (0 - Main, 1 - Process)
We can toggle only those bits and left other bits as they were on
exception entry.
It is basically, what patch does - saves EXC_RETURN when we do
transition form Thread to Handler mode (it is first svc), so later
saved value is used instead of EXC_RET_THREADMODE_PROCESSSTACK.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/kernel/entry-header.S')
| -rw-r--r-- | arch/arm/kernel/entry-header.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index 773424843d6e..62db1c9746cb 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -127,7 +127,8 @@ */ .macro v7m_exception_slow_exit ret_r0 cpsid i - ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK + ldr lr, =exc_ret + ldr lr, [lr] @ read original r12, sp, lr, pc and xPSR add r12, sp, #S_IP |