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| author |   Dinh Nguyen <dinguyen@kernel.org> | 2022-09-15 20:45:37 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2022-11-18 11:13:49 -0600 |
| commit | 31354121bf03dac6498a4236928a38490745d601 (patch) | |
| tree | e83efb74aa6e0753f70752d08434cd1ba672aab2 /arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | |
| parent | arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node (diff) | |
| download | wireguard-linux-31354121bf03dac6498a4236928a38490745d601.tar.xz wireguard-linux-31354121bf03dac6498a4236928a38490745d601.zip | |
arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts')
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 62c66e52b656..08c088571270 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -74,6 +74,7 @@ cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { |