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| author |   Baruch Siach <baruch@tkos.co.il> | 2018-10-16 13:50:53 +0300 |
|---|---|---|
| committer |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-11-30 18:44:53 +0100 |
| commit | babc5544c2933a5cbf9389679507dfa4911101ee (patch) | |
| tree | 58c2b5347c6d7c256d1f3d061138e9ed9b7cde95 /arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | |
| parent | arm64: dts: clearfog-gt-8k: fix USB regulator gpio polarity (diff) | |
| download | wireguard-linux-babc5544c2933a5cbf9389679507dfa4911101ee.tar.xz wireguard-linux-babc5544c2933a5cbf9389679507dfa4911101ee.zip | |
arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal
This reset signal controls the Marvell 1512 1G PHY.
Note that current implementation queries the PHY over the MDIO bus
(get_phy_device() call from of_mdiobus_register_phy()) before reset
signal deassert. If the PHY reset signal is asserted at boot time, PHY
registration fails. So current code relies on the bootloader to deassert
the reset signal.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index f03740d5ce62..f2e5b98f0c32 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -333,6 +333,10 @@ */ marvell,reg-init = <3 16 0 0x1017>; reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_copper_eth_phy_reset>; + reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; }; switch0: switch0@4 { |