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| author |   Baruch Siach <baruch@tkos.co.il> | 2019-02-17 20:21:40 +0200 |
|---|---|---|
| committer |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-02-19 16:09:11 +0100 |
| commit | bdd22a41d55bb0068c8685e28839ed9492e96aba (patch) | |
| tree | a00750f418de4d62d6732ab98ea5f7ee8e30f069 /arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | |
| parent | ARM: dts: armada-xp: fix Armada XP boards NAND description (diff) | |
| download | wireguard-linux-bdd22a41d55bb0068c8685e28839ed9492e96aba.tar.xz wireguard-linux-bdd22a41d55bb0068c8685e28839ed9492e96aba.zip | |
arm64: dts: clearfog-gt-8k: fix SGMII PHY reset signal
The PHY reset signal goes to mpp43 on CP0.
Fixes: babc5544c293 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal")
Reported-by: Denis Odintsov <oversun@me.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 5b4a9609e31f..2468762283a5 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -351,7 +351,7 @@ reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&cp0_copper_eth_phy_reset>; - reset-gpios = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; + reset-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; }; |