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| author |   Adam Ford <aford173@gmail.com> | 2020-12-13 12:37:54 -0600 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2020-12-28 10:46:45 +0100 |
| commit | 900d9fc3becefd050bf54c1b98e368ce6463580e (patch) | |
| tree | faa028112a18cd0841a92d9f9875e257cb00d82e /arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | |
| parent | arm64: dts: renesas: beacon: Enable SPI (diff) | |
| download | wireguard-linux-900d9fc3becefd050bf54c1b98e368ce6463580e.tar.xz wireguard-linux-900d9fc3becefd050bf54c1b98e368ce6463580e.zip | |
arm64: dts: renesas: beacon: Correct I2C bus speeds
For greater compatibility with upcoming kits that will reuse the baseboard
and SOM-level files, adjust the I2C speeds to make it the most compatible
with all devices.
Signed-off-by: Adam Ford <aford173@gmail.com>
Link: https://lore.kernel.org/r/20201213183759.223246-15-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 2a5e95ec9965..b475de38ace8 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -109,7 +109,7 @@ &i2c4 { status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; pca9654: gpio@20 { compatible = "onnn,pca9654"; |