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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-09-09 11:03:12 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-09-28 09:59:26 +0200 |
| commit | 732e8ee0351c59ded4d88106437a7ad1cff4cb83 (patch) | |
| tree | 0c5d025c5c71e2421c77c69580bc39c7b5109f7e /arch/arm64/boot/dts/renesas/draak.dtsi | |
| parent | ARM: dts: rzg1: Add missing Ethernet PHY resets (diff) | |
| download | wireguard-linux-732e8ee0351c59ded4d88106437a7ad1cff4cb83.tar.xz wireguard-linux-732e8ee0351c59ded4d88106437a7ad1cff4cb83.zip | |
arm64: dts: renesas: rcar-gen3: Add missing Ethernet PHY resets
Describe all Ethernet PHY reset GPIOs on R-Car Gen3 boards, to avoid
relying solely on boot loaders to bring PHYs out of reset.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3e6fd765850e8ef0980d8e98bc5f2126538d626f.1631177442.git.geert+renesas@glider.be
Diffstat (limited to 'arch/arm64/boot/dts/renesas/draak.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/renesas/draak.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 5f5a0bb2da86..eb0327c0df48 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -249,6 +249,7 @@ reg = <0>; interrupt-parent = <&gpio5>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>; /* * TX clock internal delay mode is required for reliable * 1Gbps communication using the KSZ9031RNX phy present on |