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| author |   Michal Simek <michal.simek@xilinx.com> | 2021-06-14 17:25:20 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-09-13 08:55:53 +0200 |
| commit | 69f8aec4f900dc8af6e38957beefcd3b763bfb5a (patch) | |
| tree | cc5536b3750790bbd0535cc3a991f3aca23142da /arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | |
| parent | arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi (diff) | |
| download | wireguard-linux-69f8aec4f900dc8af6e38957beefcd3b763bfb5a.tar.xz wireguard-linux-69f8aec4f900dc8af6e38957beefcd3b763bfb5a.zip | |
arm64: zynqmp: Add missing mio-bank properties to dc1 and dc5
Add missing mio-bank properties to zc1751 dc1 and dc5 boards.
The same change was done by commit 63481699d6e3 ("arm64: dts: zynqmp: Add
missing mio-bank properties to sdhcis").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2b2ab31639c706651dfd319f5b6bc59e68f111b6.1623684253.git.michal.simek@xilinx.com
Diffstat (limited to 'arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index 6c9460a0707c..ae2d03d98322 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -407,6 +407,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; no-1-8-v; + xlnx,mio-bank = <0>; }; &ttc0 { |