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| author |   Huacai Chen <chenhuacai@loongson.cn> | 2022-10-12 16:36:14 +0800 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-10-12 16:36:14 +0800 |
| commit | b61a40afca164a9bd066f749beff3bf209c5e209 (patch) | |
| tree | 414693038d707d37b34edfee4f4ece650275996a /arch/loongarch/include/asm/setup.h | |
| parent | LoongArch: mm: Refactor TLB exception handlers (diff) | |
| download | wireguard-linux-b61a40afca164a9bd066f749beff3bf209c5e209.tar.xz wireguard-linux-b61a40afca164a9bd066f749beff3bf209c5e209.zip | |
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm/setup.h')
| -rw-r--r-- | arch/loongarch/include/asm/setup.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/setup.h b/arch/loongarch/include/asm/setup.h index 6d7d2a3e23dd..ca373f8e3c4d 100644 --- a/arch/loongarch/include/asm/setup.h +++ b/arch/loongarch/include/asm/setup.h @@ -13,7 +13,9 @@ extern unsigned long eentry; extern unsigned long tlbrentry; +extern void tlb_init(int cpu); extern void cpu_cache_init(void); +extern void cache_error_setup(void); extern void per_cpu_trap_init(int cpu); extern void set_handler(unsigned long offset, void *addr, unsigned long len); extern void set_merr_handler(unsigned long offset, void *addr, unsigned long len); |