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| author |   Paul Mundt <lethal@linux-sh.org> | 2009-04-17 17:00:27 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-04-17 17:00:27 +0900 |
| commit | f1dcab756687622b658154ded1657538984edcdb (patch) | |
| tree | bf014b5d57be91f32bf1338113751b3f30bc2fe2 /arch/m32r/boot/compressed/m32r_sio.c | |
| parent | sh: pci: Set pci_cache_line_size on SH7780 via the PCICLS register. (diff) | |
| download | wireguard-linux-f1dcab756687622b658154ded1657538984edcdb.tar.xz wireguard-linux-f1dcab756687622b658154ded1657538984edcdb.zip | |
sh: pci: Set the I/O port base to the SH7780 I/O window default.
Presently the I/O port base isn't being set anywhere, which allows things
like generic_inl() to blow up. Fix this up to point at the PCI IO window.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/m32r/boot/compressed/m32r_sio.c')
0 files changed, 0 insertions, 0 deletions